578cc98b66
* iommu/pci/ats: arm64: dts: fvp: Enable PCIe ATS for Base RevC FVP iommu/of: Support ats-supported device-tree property dt-bindings: PCI: generic: Add ats-supported property
266 lines
6.5 KiB
C
266 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OF helpers for IOMMU
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*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/export.h>
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#include <linux/iommu.h>
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#include <linux/limits.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_iommu.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/fsl/mc.h>
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#include "iommu-priv.h"
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static int of_iommu_xlate(struct device *dev,
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struct of_phandle_args *iommu_spec)
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{
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const struct iommu_ops *ops;
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int ret;
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if (!of_device_is_available(iommu_spec->np))
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return -ENODEV;
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ret = iommu_fwspec_init(dev, of_fwnode_handle(iommu_spec->np));
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if (ret == -EPROBE_DEFER)
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return driver_deferred_probe_check_state(dev);
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if (ret)
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return ret;
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ops = iommu_ops_from_fwnode(&iommu_spec->np->fwnode);
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if (!ops->of_xlate || !try_module_get(ops->owner))
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return -ENODEV;
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ret = ops->of_xlate(dev, iommu_spec);
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module_put(ops->owner);
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return ret;
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}
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static int of_iommu_configure_dev_id(struct device_node *master_np,
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struct device *dev,
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const u32 *id)
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{
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struct of_phandle_args iommu_spec = { .args_count = 1 };
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int err;
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err = of_map_id(master_np, *id, "iommu-map",
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"iommu-map-mask", &iommu_spec.np,
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iommu_spec.args);
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if (err)
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return err;
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err = of_iommu_xlate(dev, &iommu_spec);
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of_node_put(iommu_spec.np);
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return err;
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}
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static int of_iommu_configure_dev(struct device_node *master_np,
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struct device *dev)
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{
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struct of_phandle_args iommu_spec;
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int err = -ENODEV, idx = 0;
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while (!of_parse_phandle_with_args(master_np, "iommus",
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"#iommu-cells",
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idx, &iommu_spec)) {
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err = of_iommu_xlate(dev, &iommu_spec);
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of_node_put(iommu_spec.np);
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idx++;
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if (err)
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break;
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}
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return err;
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}
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struct of_pci_iommu_alias_info {
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struct device *dev;
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struct device_node *np;
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};
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static int of_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data)
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{
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struct of_pci_iommu_alias_info *info = data;
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u32 input_id = alias;
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return of_iommu_configure_dev_id(info->np, info->dev, &input_id);
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}
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static int of_iommu_configure_device(struct device_node *master_np,
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struct device *dev, const u32 *id)
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{
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return (id) ? of_iommu_configure_dev_id(master_np, dev, id) :
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of_iommu_configure_dev(master_np, dev);
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}
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static void of_pci_check_device_ats(struct device *dev, struct device_node *np)
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{
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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if (fwspec && of_property_read_bool(np, "ats-supported"))
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fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS;
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}
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/*
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* Returns:
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* 0 on success, an iommu was configured
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* -ENODEV if the device does not have any IOMMU
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* -EPROBEDEFER if probing should be tried again
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* -errno fatal errors
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*/
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int of_iommu_configure(struct device *dev, struct device_node *master_np,
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const u32 *id)
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{
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int err;
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if (!master_np)
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return -ENODEV;
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/* Serialise to make dev->iommu stable under our potential fwspec */
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mutex_lock(&iommu_probe_device_lock);
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if (dev_iommu_fwspec_get(dev)) {
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mutex_unlock(&iommu_probe_device_lock);
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return 0;
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}
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/*
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* We don't currently walk up the tree looking for a parent IOMMU.
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* See the `Notes:' section of
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* Documentation/devicetree/bindings/iommu/iommu.txt
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*/
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if (dev_is_pci(dev)) {
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struct of_pci_iommu_alias_info info = {
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.dev = dev,
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.np = master_np,
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};
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pci_request_acs();
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err = pci_for_each_dma_alias(to_pci_dev(dev),
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of_pci_iommu_init, &info);
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of_pci_check_device_ats(dev, master_np);
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} else {
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err = of_iommu_configure_device(master_np, dev, id);
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}
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if (err)
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iommu_fwspec_free(dev);
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mutex_unlock(&iommu_probe_device_lock);
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if (!err && dev->bus)
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err = iommu_probe_device(dev);
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if (err && err != -EPROBE_DEFER)
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dev_dbg(dev, "Adding to IOMMU failed: %d\n", err);
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return err;
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}
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static enum iommu_resv_type __maybe_unused
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iommu_resv_region_get_type(struct device *dev,
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struct resource *phys,
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phys_addr_t start, size_t length)
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{
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phys_addr_t end = start + length - 1;
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/*
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* IOMMU regions without an associated physical region cannot be
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* mapped and are simply reservations.
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*/
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if (phys->start >= phys->end)
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return IOMMU_RESV_RESERVED;
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/* may be IOMMU_RESV_DIRECT_RELAXABLE for certain cases */
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if (start == phys->start && end == phys->end)
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return IOMMU_RESV_DIRECT;
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dev_warn(dev, "treating non-direct mapping [%pr] -> [%pap-%pap] as reservation\n", phys,
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&start, &end);
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return IOMMU_RESV_RESERVED;
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}
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/**
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* of_iommu_get_resv_regions - reserved region driver helper for device tree
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* @dev: device for which to get reserved regions
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* @list: reserved region list
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*
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* IOMMU drivers can use this to implement their .get_resv_regions() callback
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* for memory regions attached to a device tree node. See the reserved-memory
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* device tree bindings on how to use these:
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*
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* Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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*/
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void of_iommu_get_resv_regions(struct device *dev, struct list_head *list)
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{
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#if IS_ENABLED(CONFIG_OF_ADDRESS)
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struct of_phandle_iterator it;
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int err;
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of_for_each_phandle(&it, err, dev->of_node, "memory-region", NULL, 0) {
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const __be32 *maps, *end;
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struct resource phys;
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int size;
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memset(&phys, 0, sizeof(phys));
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/*
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* The "reg" property is optional and can be omitted by reserved-memory regions
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* that represent reservations in the IOVA space, which are regions that should
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* not be mapped.
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*/
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if (of_find_property(it.node, "reg", NULL)) {
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err = of_address_to_resource(it.node, 0, &phys);
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if (err < 0) {
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dev_err(dev, "failed to parse memory region %pOF: %d\n",
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it.node, err);
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continue;
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}
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}
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maps = of_get_property(it.node, "iommu-addresses", &size);
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if (!maps)
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continue;
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end = maps + size / sizeof(__be32);
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while (maps < end) {
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struct device_node *np;
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u32 phandle;
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phandle = be32_to_cpup(maps++);
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np = of_find_node_by_phandle(phandle);
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if (np == dev->of_node) {
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int prot = IOMMU_READ | IOMMU_WRITE;
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struct iommu_resv_region *region;
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enum iommu_resv_type type;
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phys_addr_t iova;
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size_t length;
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if (of_dma_is_coherent(dev->of_node))
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prot |= IOMMU_CACHE;
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maps = of_translate_dma_region(np, maps, &iova, &length);
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if (length == 0) {
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dev_warn(dev, "Cannot reserve IOVA region of 0 size\n");
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continue;
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}
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type = iommu_resv_region_get_type(dev, &phys, iova, length);
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region = iommu_alloc_resv_region(iova, length, prot, type,
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GFP_KERNEL);
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if (region)
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list_add_tail(®ion->list, list);
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}
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}
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}
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#endif
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}
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EXPORT_SYMBOL(of_iommu_get_resv_regions);
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