9f93a0a428
The previous wrapper qcom_cc_really_probe takes the platform device as parameter, which is limited to platform driver. As for qca8k clock controller driver, which is registered as the MDIO device, which also follows the qcom clock framework. To commonize qcom_cc_really_probe, updating it to take the struct device as parameter, so that the qcom_cc_really_probe can be utilized by the previous platform device and the new added MDIO device. Also update the current clock controller drivers to take &pdev->dev as parameter when calling qcom_cc_really_probe. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240605124541.2711467-4-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
210 lines
5.1 KiB
C
210 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
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#include "common.h"
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "gdsc.h"
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#define CX_GMU_CBCR_SLEEP_MASK 0xf
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#define CX_GMU_CBCR_SLEEP_SHIFT 4
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#define CX_GMU_CBCR_WAKE_MASK 0xf
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#define CX_GMU_CBCR_WAKE_SHIFT 8
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enum {
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P_BI_TCXO,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_CC_PLL1_OUT_MAIN,
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};
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static const struct alpha_pll_config gpu_cc_pll1_config = {
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.l = 0x1a,
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.alpha = 0xaab,
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};
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static struct clk_alpha_pll gpu_cc_pll1 = {
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.offset = 0x100,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll1",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo", .name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_fabia_ops,
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},
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},
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};
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .hw = &gpu_cc_pll1.clkr.hw },
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{ .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" },
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{ .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" },
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};
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
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F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gmu_clk_src",
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_branch gpu_cc_cx_gmu_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gmu_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_clk = {
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.halt_reg = 0x109c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x109c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cxo_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct gdsc gpu_cx_gdsc = {
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.gdscr = 0x106c,
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.gds_hw_ctrl = 0x1540,
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.clk_dis_wait_val = 0x8,
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.pd = {
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.name = "gpu_cx_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = VOTABLE,
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};
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static struct gdsc gpu_gx_gdsc = {
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.gdscr = 0x100c,
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.clamp_io_ctrl = 0x1508,
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.pd = {
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.name = "gpu_gx_gdsc",
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.power_on = gdsc_gx_do_nothing_enable,
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
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};
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static struct clk_regmap *gpu_cc_sdm845_clocks[] = {
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[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
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[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
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[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
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[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
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};
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static struct gdsc *gpu_cc_sdm845_gdscs[] = {
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[GPU_CX_GDSC] = &gpu_cx_gdsc,
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[GPU_GX_GDSC] = &gpu_gx_gdsc,
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};
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static const struct regmap_config gpu_cc_sdm845_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x8008,
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.fast_io = true,
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};
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static const struct qcom_cc_desc gpu_cc_sdm845_desc = {
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.config = &gpu_cc_sdm845_regmap_config,
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.clks = gpu_cc_sdm845_clocks,
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.num_clks = ARRAY_SIZE(gpu_cc_sdm845_clocks),
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.gdscs = gpu_cc_sdm845_gdscs,
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.num_gdscs = ARRAY_SIZE(gpu_cc_sdm845_gdscs),
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};
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static const struct of_device_id gpu_cc_sdm845_match_table[] = {
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{ .compatible = "qcom,sdm845-gpucc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table);
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static int gpu_cc_sdm845_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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unsigned int value, mask;
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regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
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/*
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* Configure gpu_cc_cx_gmu_clk with recommended
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* wakeup/sleep settings
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*/
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mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
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mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
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value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
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regmap_update_bits(regmap, 0x1098, mask, value);
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return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sdm845_desc, regmap);
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}
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static struct platform_driver gpu_cc_sdm845_driver = {
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.probe = gpu_cc_sdm845_probe,
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.driver = {
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.name = "sdm845-gpucc",
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.of_match_table = gpu_cc_sdm845_match_table,
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},
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};
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module_platform_driver(gpu_cc_sdm845_driver);
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MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver");
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MODULE_LICENSE("GPL v2");
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