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Tianyang Zhang ae16f05c92 irqchip/loongarch-avec: Add AVEC irqchip support 
Introduce the advanced extended interrupt controllers (AVECINTC). This
feature will allow each core to have 256 independent interrupt vectors
and MSI interrupts can be independently routed to any vector on any CPU.

The whole topology of irqchips in LoongArch machines looks like this if
AVECINTC is supported:

  +-----+     +-----------------------+     +-------+
  | IPI | --> |        CPUINTC        | <-- | Timer |
  +-----+     +-----------------------+     +-------+
               ^          ^          ^
               |          |          |
        +---------+ +----------+ +---------+     +-------+
        | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
        +---------+ +----------+ +---------+     +-------+
             ^            ^
             |            |
        +---------+  +---------+
        | PCH-PIC |  | PCH-MSI |
        +---------+  +---------+
          ^     ^           ^
          |     |           |
  +---------+ +---------+ +---------+
  | Devices | | PCH-LPC | | Devices |
  +---------+ +---------+ +---------+
                   ^
                   |
              +---------+
              | Devices |
              +---------+

Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Co-developed-by: Liupu Wang <wangliupu@loongson.cn>
Signed-off-by: Liupu Wang <wangliupu@loongson.cn>
Co-developed-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20240823104337.25577-2-zhangtianyang@loongson.cn
2024-08-23 20:40:27 +02:00
..
alpha
arc arc: convert to generic syscall table 2024-07-10 14:23:38 +02:00
arm Driver core changes for 6.11-rc1 2024-07-25 10:42:22 -07:00
arm64 RISC-V Patches for the 6.11 Merge Window, Part 2 2024-07-27 10:14:34 -07:00
csky ftrace: Rewrite of function graph tracer 2024-07-18 13:36:33 -07:00
hexagon hexagon: use new system call table 2024-07-10 14:23:38 +02:00
loongarch irqchip/loongarch-avec: Add AVEC irqchip support 2024-08-23 20:40:27 +02:00
m68k Kbuild updates for v6.11 2024-07-23 14:32:21 -07:00
microblaze
mips - Use improved timer sync for Loongson64 2024-07-25 12:41:53 -07:00
nios2 Kbuild updates for v6.11 2024-07-23 14:32:21 -07:00
openrisc openrisc: convert to generic syscall table 2024-07-10 14:23:38 +02:00
parisc parisc architecture fixes and updates for kernel v6.11-rc1: 2024-07-25 12:37:42 -07:00
powerpc Devicetree fixes for 6.11, part 1 2024-07-27 12:46:16 -07:00
riscv RISC-V Patches for the 6.11 Merge Window, Part 2 2024-07-27 10:14:34 -07:00
s390 more s390 updates for 6.11 merge window 2024-07-26 10:47:53 -07:00
sh sh updates for v6.11 2024-07-23 11:57:52 -07:00
sparc Driver core changes for 6.11-rc1 2024-07-25 10:42:22 -07:00
um This pull request contains the following changes for UML: 2024-07-25 12:33:08 -07:00
x86 minmax: add a few more MIN_T/MAX_T users 2024-07-28 13:41:14 -07:00
xtensa - 875fa64577da ("mm/hugetlb_vmemmap: fix race with speculative PFN 2024-07-21 17:15:46 -07:00
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