- Use improved timer sync for Loongson64
- Fix address of GCR_ACCESS register - Add missing MODULE_DESCRIPTION -----BEGIN PGP SIGNATURE----- iQJOBAABCAA4FiEEbt46xwy6kEcDOXoUeZbBVTGwZHAFAmaieCgaHHRzYm9nZW5k QGFscGhhLmZyYW5rZW4uZGUACgkQeZbBVTGwZHDwCw/+JCKVax/0Gu3RYsL3cOsA fVSiy51x97ZuVlzLTdiQb3ZUrPY2Rw1/q3GPrdJx6ahVZoFyc8kETVszW7HyBhXU fh1PABDW+SHNW+j/mcm3o6YkCtX0MCfZLWEEPgnSWTFSedSYuRmeY1a9nAr+LhgU pJsrDOaDhCScKhGimkXinTAYjSdMLOUwHwcN2f8JeX5nBErpkcWN9v09tW8jyc/w pM85wEk4ZmGqoU1yQI+iIYp4iokyAN5M6NrvzCKwRyTijg0+lxIw9br2vPkPj/aF 6gWQoOr94g7yCqzF9dIzP6UvlJLV6NE1zq8BQgh3UtdGC7ZPocnOnZCs58PUtZ5B aZDZ0P7NN9FQ3zmSGuzOgj+5n720AbiL1qZJyA62Y1sgygyUjtSGAsygw7pm8yBH JdMrU+IAcR5HWwGpM7AkOUE3b4ZewbjFXBSwxVboiVfnDzRS4dkX0Xyi1CRAEmCl /sra/Aizb9D8TWygcknJf0qzKRERkI/J8j+TY94fAchHCiGFpk4bNkDx7BaqvVCw OSjPd/x1nusMmg2Th0i9Gr2mZMHSnapJdfS6RN+vfOyMQdURAuz10zG1Tlfv84IQ SJ+oYtGDFmPFK6jeDL7KRzyqQdOzZ5jdajMQ0Vgjy7esacmZVSxO25xysR85MqEM 9cVwznhhy8nN/DdJPd4XraA= =qtYd -----END PGP SIGNATURE----- Merge tag 'mips_6.11_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Thomas Bogendoerfer: - Use improved timer sync for Loongson64 - Fix address of GCR_ACCESS register - Add missing MODULE_DESCRIPTION * tag 'mips_6.11_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: mips: sibyte: add missing MODULE_DESCRIPTION() macro MIPS: SMP-CPS: Fix address for GCR_ACCESS register for CM3 and later MIPS: Loongson64: Switch to SYNC_R4K
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commit
28e7241cb8
@ -478,6 +478,7 @@ config MACH_LOONGSON64
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select BOARD_SCACHE
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select CSRC_R4K
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select CEVT_R4K
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select SYNC_R4K
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select FORCE_PCI
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select ISA
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select I8259
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@ -240,6 +240,10 @@ GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
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GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
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#define CM_GCR_CPC_STATUS_EX BIT(0)
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/* GCR_ACCESS - Controls core/IOCU access to GCRs */
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GCR_ACCESSOR_RW(32, 0x120, access_cm3)
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#define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)
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/* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
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GCR_ACCESSOR_RW(32, 0x130, l2_config)
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#define CM_GCR_L2_CONFIG_BYPASS BIT(20)
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@ -50,7 +50,6 @@ extern int __cpu_logical_map[NR_CPUS];
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#define SMP_CALL_FUNCTION 0x2
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/* Octeon - Tell another core to flush its icache */
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#define SMP_ICACHE_FLUSH 0x4
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#define SMP_ASK_C0COUNT 0x8
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/* Mask of CPUs which are currently definitely operating coherently */
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extern cpumask_t cpu_coherent_mask;
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@ -317,7 +317,10 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
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write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
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/* Ensure the core can access the GCRs */
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set_gcr_access(1 << core);
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if (mips_cm_revision() < CM_REV_CM3)
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set_gcr_access(1 << core);
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else
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set_gcr_access_cm3(1 << core);
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if (mips_cpc_present()) {
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/* Reset the core */
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@ -33,7 +33,6 @@ static void __iomem *ipi_clear0_regs[16];
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static void __iomem *ipi_status0_regs[16];
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static void __iomem *ipi_en0_regs[16];
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static void __iomem *ipi_mailbox_buf[16];
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static uint32_t core0_c0count[NR_CPUS];
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static u32 (*ipi_read_clear)(int cpu);
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static void (*ipi_write_action)(int cpu, u32 action);
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@ -382,11 +381,10 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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ipi_write_action(cpu_logical_map(i), (u32)action);
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}
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static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
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{
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int i, cpu = smp_processor_id();
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unsigned int action, c0count;
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int cpu = smp_processor_id();
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unsigned int action;
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action = ipi_read_clear(cpu);
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@ -399,26 +397,14 @@ static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
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irq_exit();
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}
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if (action & SMP_ASK_C0COUNT) {
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BUG_ON(cpu != 0);
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c0count = read_c0_count();
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c0count = c0count ? c0count : 1;
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for (i = 1; i < nr_cpu_ids; i++)
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core0_c0count[i] = c0count;
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nudge_writes(); /* Let others see the result ASAP */
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}
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return IRQ_HANDLED;
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}
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#define MAX_LOOPS 800
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/*
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* SMP init and finish on secondary CPUs
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*/
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static void loongson3_init_secondary(void)
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{
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int i;
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uint32_t initcount;
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unsigned int cpu = smp_processor_id();
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unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |
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STATUSF_IP3 | STATUSF_IP2;
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@ -432,23 +418,6 @@ static void loongson3_init_secondary(void)
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cpu_logical_map(cpu) % loongson_sysconf.cores_per_package);
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cpu_data[cpu].package =
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cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
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i = 0;
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core0_c0count[cpu] = 0;
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loongson3_send_ipi_single(0, SMP_ASK_C0COUNT);
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while (!core0_c0count[cpu]) {
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i++;
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cpu_relax();
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}
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if (i > MAX_LOOPS)
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i = MAX_LOOPS;
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if (cpu_data[cpu].package)
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initcount = core0_c0count[cpu] + i;
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else /* Local access is faster for loops */
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initcount = core0_c0count[cpu] + i/2;
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write_c0_count(initcount);
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}
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static void loongson3_smp_finish(void)
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@ -589,4 +589,5 @@ module_exit(sbprof_tb_cleanup);
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MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR);
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MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
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MODULE_DESCRIPTION("Support for ZBbus profiling");
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MODULE_LICENSE("GPL");
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