b0ef3434da
On some of Qualcomm platforms the Global Clock Controller (GCC) doesn't provide power domains. Move requirement for the '#power-domain-cells' out of the common qcom,gcc.yaml into individual schema files. For the platforms that do not provide power-domains, explicitly forbid having the '#power-domain-cells' property. Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-2-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
74 lines
1.8 KiB
YAML
74 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on X1E80100
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maintainers:
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- Rajendra Nayak <quic_rjendra@quicinc.com>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on X1E80100
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See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h
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properties:
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compatible:
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const: qcom,x1e80100-gcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: PCIe 3 pipe clock
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- description: PCIe 4 pipe clock
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- description: PCIe 5 pipe clock
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- description: PCIe 6a pipe clock
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- description: PCIe 6b pipe clock
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- description: USB QMP Phy 0 clock source
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- description: USB QMP Phy 1 clock source
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- description: USB QMP Phy 2 clock source
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power-domains:
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description:
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A phandle and PM domain specifier for the CX power domain.
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maxItems: 1
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required:
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- compatible
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- clocks
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- power-domains
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/power/qcom,rpmhpd.h>
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clock-controller@100000 {
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compatible = "qcom,x1e80100-gcc";
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reg = <0x00100000 0x200000>;
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clocks = <&bi_tcxo_div2>,
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<&sleep_clk>,
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<&pcie3_phy>,
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<&pcie4_phy>,
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<&pcie5_phy>,
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<&pcie6a_phy>,
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<&pcie6b_phy>,
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<&usb_1_ss0_qmpphy 0>,
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<&usb_1_ss1_qmpphy 1>,
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<&usb_1_ss2_qmpphy 2>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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