2023-12-04 23:09:59 -07:00
|
|
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
|
|
%YAML 1.2
|
|
|
|
---
|
|
|
|
$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
|
|
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
|
|
|
|
title: Qualcomm Global Clock & Reset Controller on X1E80100
|
|
|
|
|
|
|
|
maintainers:
|
|
|
|
- Rajendra Nayak <quic_rjendra@quicinc.com>
|
|
|
|
|
|
|
|
description: |
|
|
|
|
Qualcomm global clock control module provides the clocks, resets and power
|
|
|
|
domains on X1E80100
|
|
|
|
|
|
|
|
See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h
|
|
|
|
|
|
|
|
properties:
|
|
|
|
compatible:
|
|
|
|
const: qcom,x1e80100-gcc
|
|
|
|
|
|
|
|
clocks:
|
|
|
|
items:
|
|
|
|
- description: Board XO source
|
|
|
|
- description: Sleep clock source
|
|
|
|
- description: PCIe 3 pipe clock
|
|
|
|
- description: PCIe 4 pipe clock
|
|
|
|
- description: PCIe 5 pipe clock
|
|
|
|
- description: PCIe 6a pipe clock
|
|
|
|
- description: PCIe 6b pipe clock
|
|
|
|
- description: USB QMP Phy 0 clock source
|
|
|
|
- description: USB QMP Phy 1 clock source
|
|
|
|
- description: USB QMP Phy 2 clock source
|
|
|
|
|
|
|
|
power-domains:
|
|
|
|
description:
|
|
|
|
A phandle and PM domain specifier for the CX power domain.
|
|
|
|
maxItems: 1
|
|
|
|
|
|
|
|
required:
|
|
|
|
- compatible
|
|
|
|
- clocks
|
|
|
|
- power-domains
|
2024-05-29 07:47:00 -07:00
|
|
|
- '#power-domain-cells'
|
2023-12-04 23:09:59 -07:00
|
|
|
|
|
|
|
allOf:
|
|
|
|
- $ref: qcom,gcc.yaml#
|
|
|
|
|
|
|
|
unevaluatedProperties: false
|
|
|
|
|
|
|
|
examples:
|
|
|
|
- |
|
|
|
|
#include <dt-bindings/power/qcom,rpmhpd.h>
|
|
|
|
clock-controller@100000 {
|
|
|
|
compatible = "qcom,x1e80100-gcc";
|
|
|
|
reg = <0x00100000 0x200000>;
|
|
|
|
clocks = <&bi_tcxo_div2>,
|
|
|
|
<&sleep_clk>,
|
|
|
|
<&pcie3_phy>,
|
|
|
|
<&pcie4_phy>,
|
|
|
|
<&pcie5_phy>,
|
|
|
|
<&pcie6a_phy>,
|
|
|
|
<&pcie6b_phy>,
|
|
|
|
<&usb_1_ss0_qmpphy 0>,
|
|
|
|
<&usb_1_ss1_qmpphy 1>,
|
|
|
|
<&usb_1_ss2_qmpphy 2>;
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
#clock-cells = <1>;
|
|
|
|
#reset-cells = <1>;
|
|
|
|
#power-domain-cells = <1>;
|
|
|
|
};
|
|
|
|
|
|
|
|
...
|