2453e858e9
On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK signal is selectable to support an Ethernet PHY operating in either MII or RGMII mode. By default, the signal is configured as an input and MII mode is supported. The ETH_MODE register can be modified to configure this signal as an output to support RGMII mode. As this signal is by default an input, and can optionally be switched to an output, it maps neatly onto an `output-enable` property in the device tree. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240625200316.4282-4-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
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| .. | ||
| core.c | ||
| core.h | ||
| gpio.c | ||
| Kconfig | ||
| Makefile | ||
| pfc-emev2.c | ||
| pfc-r8a73a4.c | ||
| pfc-r8a779a0.c | ||
| pfc-r8a779f0.c | ||
| pfc-r8a779g0.c | ||
| pfc-r8a779h0.c | ||
| pfc-r8a7740.c | ||
| pfc-r8a7778.c | ||
| pfc-r8a7779.c | ||
| pfc-r8a7790.c | ||
| pfc-r8a7791.c | ||
| pfc-r8a7792.c | ||
| pfc-r8a7794.c | ||
| pfc-r8a7796.c | ||
| pfc-r8a77470.c | ||
| pfc-r8a77951.c | ||
| pfc-r8a77965.c | ||
| pfc-r8a77970.c | ||
| pfc-r8a77980.c | ||
| pfc-r8a77990.c | ||
| pfc-r8a77995.c | ||
| pfc-sh73a0.c | ||
| pfc-sh7203.c | ||
| pfc-sh7264.c | ||
| pfc-sh7269.c | ||
| pfc-sh7720.c | ||
| pfc-sh7722.c | ||
| pfc-sh7723.c | ||
| pfc-sh7724.c | ||
| pfc-sh7734.c | ||
| pfc-sh7757.c | ||
| pfc-sh7785.c | ||
| pfc-sh7786.c | ||
| pfc-shx3.c | ||
| pinctrl-rza1.c | ||
| pinctrl-rza2.c | ||
| pinctrl-rzg2l.c | ||
| pinctrl-rzn1.c | ||
| pinctrl-rzv2m.c | ||
| pinctrl.c | ||
| sh_pfc.h | ||