734f69a773
Move the DVFS virtual clock functions from clock2xxx.c to mach-omap2/clkt2xxx_virt_prcm_set.c. This is intended to make the clock code easier to understand, since all of the functions needed to manage the virt_prcm_set clock are now located in their own file, rather than being mixed with other, unrelated functions. Clock debugging is also now more finely-grained, since the DEBUG macro can now be defined for the virt_prcm_set clock alone. This should reduce unnecessary console noise when debugging. Also, if at some future point the mach-omap2/ directory is split into OMAP2/3/4 variants, this clkt file can be placed in the mach-omap2xxx/ directory, rather than shared with other chip types that don't use this clock type. Thanks to Alexander Shishkin <virtuoso@slind.org> for his comments. Thanks also to Kevin Hilman <khilman@deeprootsystems.com> for finding and fixing a bug with the CONFIG_CPU_FREQ portion of this patch. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Alexander Shishkin <virtuoso@slind.org> Cc: Kevin Hilman <khilman@deeprootsystems.com>
273 lines
6.3 KiB
C
273 lines
6.3 KiB
C
/*
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* linux/arch/arm/mach-omap2/clock.c
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2008 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
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* Gordon McNutt and RidgeRun, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/cpufreq.h>
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#include <linux/bitops.h>
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#include <plat/clock.h>
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#include <plat/sram.h>
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#include <plat/prcm.h>
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#include <plat/clkdev_omap.h>
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#include <asm/div64.h>
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#include <asm/clkdev.h>
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#include <plat/sdrc.h>
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#include "clock.h"
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#include "clock2xxx.h"
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#include "opp2xxx.h"
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#include "prm.h"
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#include "prm-regbits-24xx.h"
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#include "cm.h"
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#include "cm-regbits-24xx.h"
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/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
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#define EN_APLL_STOPPED 0
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#define EN_APLL_LOCKED 3
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/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
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#define APLLS_CLKIN_19_2MHZ 0
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#define APLLS_CLKIN_13MHZ 2
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#define APLLS_CLKIN_12MHZ 3
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struct clk *vclk, *sclk, *dclk;
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void __iomem *prcm_clksrc_ctrl;
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/*-------------------------------------------------------------------------
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* Omap24xx specific clock functions
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*-------------------------------------------------------------------------*/
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/**
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* omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
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* @clk: struct clk * being enabled
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* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
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* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
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*
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* OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
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* CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
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* passes back the correct CM_IDLEST register address for I2CHS
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* modules. No return value.
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*/
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static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
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void __iomem **idlest_reg,
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u8 *idlest_bit)
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{
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*idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
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*idlest_bit = clk->enable_bit;
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}
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/* 2430 I2CHS has non-standard IDLEST register */
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const struct clkops clkops_omap2430_i2chs_wait = {
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.enable = omap2_dflt_clk_enable,
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.disable = omap2_dflt_clk_disable,
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.find_idlest = omap2430_clk_i2chs_find_idlest,
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.find_companion = omap2_clk_dflt_find_companion,
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};
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static int omap2_enable_osc_ck(struct clk *clk)
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{
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u32 pcc;
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pcc = __raw_readl(prcm_clksrc_ctrl);
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__raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
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return 0;
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}
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static void omap2_disable_osc_ck(struct clk *clk)
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{
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u32 pcc;
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pcc = __raw_readl(prcm_clksrc_ctrl);
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__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
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}
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const struct clkops clkops_oscck = {
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.enable = omap2_enable_osc_ck,
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.disable = omap2_disable_osc_ck,
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};
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#ifdef OLD_CK
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/* Recalculate SYST_CLK */
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static void omap2_sys_clk_recalc(struct clk *clk)
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{
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u32 div = PRCM_CLKSRC_CTRL;
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div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
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div >>= clk->rate_offset;
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clk->rate = (clk->parent->rate / div);
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propagate_rate(clk);
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}
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#endif /* OLD_CK */
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/* Enable an APLL if off */
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static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
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{
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u32 cval, apll_mask;
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apll_mask = EN_APLL_LOCKED << clk->enable_bit;
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cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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if ((cval & apll_mask) == apll_mask)
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return 0; /* apll already enabled */
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cval &= ~apll_mask;
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cval |= apll_mask;
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cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
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omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
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clk->name);
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/*
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* REVISIT: Should we return an error code if omap2_wait_clock_ready()
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* fails?
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*/
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return 0;
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}
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static int omap2_clk_apll96_enable(struct clk *clk)
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{
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return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
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}
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static int omap2_clk_apll54_enable(struct clk *clk)
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{
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return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
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}
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/* Stop APLL */
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static void omap2_clk_apll_disable(struct clk *clk)
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{
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u32 cval;
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cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
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cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
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}
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const struct clkops clkops_apll96 = {
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.enable = omap2_clk_apll96_enable,
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.disable = omap2_clk_apll_disable,
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};
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const struct clkops clkops_apll54 = {
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.enable = omap2_clk_apll54_enable,
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.disable = omap2_clk_apll_disable,
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};
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static u32 omap2_get_apll_clkin(void)
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{
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u32 aplls, srate = 0;
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aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
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aplls &= OMAP24XX_APLLS_CLKIN_MASK;
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aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
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if (aplls == APLLS_CLKIN_19_2MHZ)
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srate = 19200000;
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else if (aplls == APLLS_CLKIN_13MHZ)
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srate = 13000000;
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else if (aplls == APLLS_CLKIN_12MHZ)
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srate = 12000000;
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return srate;
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}
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static u32 omap2_get_sysclkdiv(void)
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{
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u32 div;
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div = __raw_readl(prcm_clksrc_ctrl);
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div &= OMAP_SYSCLKDIV_MASK;
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div >>= OMAP_SYSCLKDIV_SHIFT;
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return div;
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}
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unsigned long omap2_osc_clk_recalc(struct clk *clk)
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{
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return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
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}
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unsigned long omap2_sys_clk_recalc(struct clk *clk)
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{
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return clk->parent->rate / omap2_get_sysclkdiv();
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}
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/*
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* Set clocks for bypass mode for reboot to work.
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*/
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void omap2_clk_prepare_for_reboot(void)
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{
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u32 rate;
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if (vclk == NULL || sclk == NULL)
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return;
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rate = clk_get_rate(sclk);
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clk_set_rate(vclk, rate);
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}
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/*
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* Switch the MPU rate if specified on cmdline.
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* We cannot do this early until cmdline is parsed.
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*/
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static int __init omap2_clk_arch_init(void)
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{
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struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck;
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unsigned long sys_ck_rate;
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if (!mpurate)
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return -EINVAL;
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virt_prcm_set = clk_get(NULL, "virt_prcm_set");
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sys_ck = clk_get(NULL, "sys_ck");
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dpll_ck = clk_get(NULL, "dpll_ck");
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mpu_ck = clk_get(NULL, "mpu_ck");
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if (clk_set_rate(virt_prcm_set, mpurate))
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printk(KERN_ERR "Could not find matching MPU rate\n");
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recalculate_root_clocks();
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sys_ck_rate = clk_get_rate(sys_ck);
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pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): "
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"%ld.%01ld/%ld/%ld MHz\n",
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(sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10,
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(clk_get_rate(dpll_ck) / 1000000),
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(clk_get_rate(mpu_ck) / 1000000));
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return 0;
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}
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arch_initcall(omap2_clk_arch_init);
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