Linus Torvalds 0bfbc914d9 RISC-V Patches for the 6.10 Merge Window, Part 1 ... * Support for byte/half-word compare-and-exchange, emulated via LR/SC loops. * Support for Rust. * Support for Zihintpause in hwprobe. * Support for the PR_RISCV_SET_ICACHE_FLUSH_CTX prctl(). * Support for lockless lockrefs. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmZN/hcTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiVrGEACUT3gsbTx1q7fa11iQNxOjVkpl66Qn 7+kI+V9xt5+GuH2EjJk6AsSNHPKeQ8totbSTA8AZjINFvgVjXslN+DPpcjCFKvnh NN5/Lyd64X0PZMsxGWlN9SHTFWf2b7lalCnY51BlX/IpBbHWc/no9XUsPSVixx6u 9q+JoS3D1DDV92nGcA/UK9ICCsDcf4omWgZW7KbjnVWnuY9jt4ctTy11jtF2RM9R Z9KAWh0RqPzjz0vNbBBf9Iw7E4jt/Px6HDYPfZAiE2dVsCTHjdsC7TcGRYXzKt6F 4q9zg8kzwvUG5GaBl7/XprXO1vaeOUmPcTVoE7qlRkSdkknRH/iBz1P4hk+r0fze f+h5ZUV/oJP7vDb+vHm/BExtGufgLuJ2oMA2Bp9qI17EMcMsGiRMt7DsBMEafWDk bNrFcJdqqYBz6HxfTwzNH5ErxfS/59PuwYl913BTSOH//raCZCFXOfyrSICH7qXd UFOLLmBpMuApLa8ayFeI9Mp3flWfbdQHR52zLRLiUvlpWNEDKrNQN417juVwTXF0 DYkjJDhFPLfFOr/sJBboftOMOUdA9c/CJepY9o4kPvBXUvPtRHN1jdXDNSCVDZRb nErnsJ9rv0PzfxQU7Xjhd2QmCMeMlbCQDpXAKKETyyimpTbgF33rovN0i5ixX3m4 KG6RvKDubOzZdA== =YLoD -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Add byte/half-word compare-and-exchange, emulated via LR/SC loops - Support for Rust - Support for Zihintpause in hwprobe - Add PR_RISCV_SET_ICACHE_FLUSH_CTX prctl() - Support lockless lockrefs * tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits) riscv: defconfig: Enable CONFIG_CLK_SOPHGO_CV1800 riscv: select ARCH_HAS_FAST_MULTIPLIER riscv: mm: still create swiotlb buffer for kmalloc() bouncing if required riscv: Annotate pgtable_l{4,5}_enabled with __ro_after_init riscv: Remove redundant CONFIG_64BIT from pgtable_l{4,5}_enabled riscv: mm: Always use an ASID to flush mm contexts riscv: mm: Preserve global TLB entries when switching contexts riscv: mm: Make asid_bits a local variable riscv: mm: Use a fixed layout for the MM context ID riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: mm: Combine the SMP and UP TLB flush code riscv: Only send remote fences when some other CPU is online riscv: mm: Broadcast kernel TLB flushes only when needed riscv: Use IPIs for remote cache/TLB flushes by default riscv: Factor out page table TLB synchronization riscv: Flush the instruction cache during SMP bringup riscv: hwprobe: export Zihintpause ISA extension riscv: misaligned: remove CONFIG_RISCV_M_MODE specific code ...		2024-05-22 09:56:00 -07:00
..
cache-ops.c	riscv: split cache ops out of dma-noncoherent.c	2023-11-07 09:37:42 -08:00
cacheflush.c	Merge patch series "riscv: ASID-related and UP-related TLB flush enhancements"	2024-04-30 10:35:48 -07:00
context.c	Merge patch series "riscv: ASID-related and UP-related TLB flush enhancements"	2024-04-30 10:35:48 -07:00
dma-noncoherent.c	dma-mapping: Simplify arch_setup_dma_ops()	2024-04-26 12:07:28 +02:00
extable.c	riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HW	2024-01-09 20:18:20 -08:00
fault.c	riscv: mm: accelerate pagefault when badaccess	2024-04-25 20:56:39 -07:00
hugetlbpage.c	mm/treewide: remove pXd_huge()	2024-04-25 20:55:47 -07:00
init.c	RISC-V Patches for the 6.10 Merge Window, Part 1	2024-05-22 09:56:00 -07:00
kasan_init.c	percpu:	2024-01-18 15:01:28 -08:00
Makefile	riscv: mm: Combine the SMP and UP TLB flush code	2024-04-29 10:49:29 -07:00
pageattr.c	Merge remote-tracking branch 'palmer/fixes' into for-next	2024-01-09 20:10:32 -08:00
pgtable.c	riscv: Only flush the mm icache when setting an exec pte	2024-03-20 08:56:08 -07:00
physaddr.c
pmem.c
ptdump.c	mm: ptdump: have ptdump_check_wx() return bool	2024-02-22 10:24:47 -08:00
tlbflush.c	RISC-V Patches for the 6.10 Merge Window, Part 1	2024-05-22 09:56:00 -07:00