ac7473a179
- Core: - Provide a new mechanism to create interrupt domains. The existing interfaces have already too many parameters and it's a pain to expand any of this for new required functionality. The new function takes a pointer to a data structure as argument. The data structure combines all existing parameters and allows for easy extension. The first extension for this is to handle the instantiation of generic interrupt chips at the core level and to allow drivers to provide extra init/exit callbacks. This is necessary to do the full interrupt chip initialization before the new domain is published, so that concurrent usage sites won't see a half initialized interrupt domain. Similar problems exist on teardown. This has turned out to be a real problem due to the deferred and parallel probing which was added in recent years. Handling this at the core level allows to remove quite some accrued boilerplate code in existing drivers and avoids horrible workarounds at the driver level. - The usual small improvements all over the place - Drivers - Add support for LAN966x OIC and RZ/Five SoC - Split the STM ExtI driver into a microcontroller and a SMP version to allow building the latter as a module for multi-platform kernels. - Enable MSI support for Armada 370XP on platforms which do not support IPIs. - The usual small fixes and enhancements all over the place. -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmaVJbUTHHRnbHhAbGlu dXRyb25peC5kZQAKCRCmGPVMDXSYoXTuD/9Tc9BhY5CW7HQkdPQu2Db1O+esprkQ Uo9lMpTTpPiy9btg4LONzLf4mjbufZpyKBxkRWoZFO0Zj5q4UE9NZYh7EcxrF5Tl CIFJmyteLsYuOyCmPrtSDSovonXjQKYBE3u2LVJNNkwEkhYbYW9sqIKeT8nneLv6 53gd28ESFUEUjHNTblw/eXviweyUKSXc0qyg+3hgZQPMoh9RkdkEPvyaw9Y/s5Ce FelLLxzMqX86dR2TJMLqiaGiMpUu/kl+Yz2m5c77TwA2D68qjhHywbtKtlH7b3C6 LMHu2dMrrKSJrLL8roVIYJdHAd1TKWVdnYhqv9WBHFTu1sDuztpR44mewbo8exUU L2RgVSGYNmeFC3p4wztWYSQfIVa9uOg7+TnJJdh7G0jLIeKM/TbufWqDAJAuoVPL QhGbZ5xNbZJZ8bvhhItjxpRN/kPs44p3mUGyRJBQzm+mDN118bqfmQzhLcwRbfE2 smp73SQzg9alG2rGdNVEqkKmp8zhg2Crx2VCeVdgbeOxWQRet9zLWcp4FfCEUE9e eK3iEi8z+rmwafaf3rsxYdrdIRLaUmcni0v7R/16cJH/Cs7bU3Re8XyGhevo3lsO pJiP5wZDxbckwXNpLm3S/qPDW7vSCnuFPF7QmOvC3a70PsD+E4NKUgiwJuHtn/ZV pFBKzbQgCsowQA== =QCRH -----END PGP SIGNATURE----- Merge tag 'irq-core-2024-07-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull interrupt subsystem updates from Thomas Gleixner: "Core: - Provide a new mechanism to create interrupt domains. The existing interfaces have already too many parameters and it's a pain to expand any of this for new required functionality. The new function takes a pointer to a data structure as argument. The data structure combines all existing parameters and allows for easy extension. The first extension for this is to handle the instantiation of generic interrupt chips at the core level and to allow drivers to provide extra init/exit callbacks. This is necessary to do the full interrupt chip initialization before the new domain is published, so that concurrent usage sites won't see a half initialized interrupt domain. Similar problems exist on teardown. This has turned out to be a real problem due to the deferred and parallel probing which was added in recent years. Handling this at the core level allows to remove quite some accrued boilerplate code in existing drivers and avoids horrible workarounds at the driver level. - The usual small improvements all over the place Drivers: - Add support for LAN966x OIC and RZ/Five SoC - Split the STM ExtI driver into a microcontroller and a SMP version to allow building the latter as a module for multi-platform kernels - Enable MSI support for Armada 370XP on platforms which do not support IPIs - The usual small fixes and enhancements all over the place" * tag 'irq-core-2024-07-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (59 commits) irqdomain: Fix the kernel-doc and plug it into Documentation genirq: Set IRQF_COND_ONESHOT in request_irq() irqchip/imx-irqsteer: Handle runtime power management correctly irqchip/gic-v3: Pass #redistributor-regions to gic_of_setup_kvm_info() irqchip/bcm2835: Enable SKIP_SET_WAKE and MASK_ON_SUSPEND irqchip/gic-v4: Make sure a VPE is locked when VMAPP is issued irqchip/gic-v4: Substitute vmovp_lock for a per-VM lock irqchip/gic-v4: Always configure affinity on VPE activation Revert "irqchip/dw-apb-ictl: Support building as module" Revert "Loongarch: Support loongarch avec" arm64: Kconfig: Allow build irq-stm32mp-exti driver as module ARM: stm32: Allow build irq-stm32mp-exti driver as module irqchip/stm32mp-exti: Allow building as module irqchip/stm32mp-exti: Rename internal symbols irqchip/stm32-exti: Split MCU and MPU code arm64: Kconfig: Select STM32MP_EXTI on STM32 platforms ARM: stm32: Use different EXTI driver on ARMv7m and ARMv7a irqchip/stm32-exti: Add CONFIG_STM32MP_EXTI irqchip/dw-apb-ictl: Support building as module irqchip/riscv-aplic: Simplify the initialization code ...
430 lines
11 KiB
C
430 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2005 Intel Corporation
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* Copyright (C) 2009 Hewlett-Packard Development Company, L.P.
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*
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* Alex Chiang <achiang@hp.com>
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* - Unified x86/ia64 implementations
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*
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* I/O APIC hotplug support
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* Yinghai Lu <yinghai@kernel.org>
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* Jiang Liu <jiang.liu@intel.com>
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*/
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#include <linux/export.h>
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#include <linux/acpi.h>
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#include <acpi/processor.h>
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static struct acpi_table_madt *get_madt_table(void)
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{
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static struct acpi_table_madt *madt;
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static int read_madt;
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if (!read_madt) {
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if (ACPI_FAILURE(acpi_get_table(ACPI_SIG_MADT, 0,
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(struct acpi_table_header **)&madt)))
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madt = NULL;
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read_madt++;
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}
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return madt;
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}
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static int map_lapic_id(struct acpi_subtable_header *entry,
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u32 acpi_id, phys_cpuid_t *apic_id)
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{
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struct acpi_madt_local_apic *lapic =
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container_of(entry, struct acpi_madt_local_apic, header);
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if (!(lapic->lapic_flags & ACPI_MADT_ENABLED))
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return -ENODEV;
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if (lapic->processor_id != acpi_id)
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return -EINVAL;
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*apic_id = lapic->id;
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return 0;
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}
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static int map_x2apic_id(struct acpi_subtable_header *entry,
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int device_declaration, u32 acpi_id, phys_cpuid_t *apic_id)
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{
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struct acpi_madt_local_x2apic *apic =
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container_of(entry, struct acpi_madt_local_x2apic, header);
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if (!(apic->lapic_flags & ACPI_MADT_ENABLED))
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return -ENODEV;
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if (device_declaration && (apic->uid == acpi_id)) {
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*apic_id = apic->local_apic_id;
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return 0;
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}
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return -EINVAL;
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}
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static int map_lsapic_id(struct acpi_subtable_header *entry,
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int device_declaration, u32 acpi_id, phys_cpuid_t *apic_id)
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{
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struct acpi_madt_local_sapic *lsapic =
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container_of(entry, struct acpi_madt_local_sapic, header);
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if (!(lsapic->lapic_flags & ACPI_MADT_ENABLED))
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return -ENODEV;
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if (device_declaration) {
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if ((entry->length < 16) || (lsapic->uid != acpi_id))
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return -EINVAL;
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} else if (lsapic->processor_id != acpi_id)
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return -EINVAL;
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*apic_id = (lsapic->id << 8) | lsapic->eid;
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return 0;
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}
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/*
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* Retrieve the ARM CPU physical identifier (MPIDR)
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*/
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static int map_gicc_mpidr(struct acpi_subtable_header *entry,
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int device_declaration, u32 acpi_id, phys_cpuid_t *mpidr)
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{
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struct acpi_madt_generic_interrupt *gicc =
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container_of(entry, struct acpi_madt_generic_interrupt, header);
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if (!(gicc->flags &
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(ACPI_MADT_ENABLED | ACPI_MADT_GICC_ONLINE_CAPABLE)))
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return -ENODEV;
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/* device_declaration means Device object in DSDT, in the
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* GIC interrupt model, logical processors are required to
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* have a Processor Device object in the DSDT, so we should
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* check device_declaration here
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*/
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if (device_declaration && (gicc->uid == acpi_id)) {
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*mpidr = gicc->arm_mpidr;
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return 0;
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}
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return -EINVAL;
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}
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/*
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* Retrieve the RISC-V hartid for the processor
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*/
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static int map_rintc_hartid(struct acpi_subtable_header *entry,
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int device_declaration, u32 acpi_id,
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phys_cpuid_t *hartid)
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{
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struct acpi_madt_rintc *rintc =
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container_of(entry, struct acpi_madt_rintc, header);
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if (!(rintc->flags & ACPI_MADT_ENABLED))
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return -ENODEV;
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/* device_declaration means Device object in DSDT, in the
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* RISC-V, logical processors are required to
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* have a Processor Device object in the DSDT, so we should
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* check device_declaration here
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*/
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if (device_declaration && rintc->uid == acpi_id) {
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*hartid = rintc->hart_id;
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return 0;
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}
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return -EINVAL;
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}
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/*
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* Retrieve LoongArch CPU physical id
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*/
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static int map_core_pic_id(struct acpi_subtable_header *entry,
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int device_declaration, u32 acpi_id, phys_cpuid_t *phys_id)
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{
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struct acpi_madt_core_pic *core_pic =
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container_of(entry, struct acpi_madt_core_pic, header);
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if (!(core_pic->flags & ACPI_MADT_ENABLED))
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return -ENODEV;
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/* device_declaration means Device object in DSDT, in LoongArch
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* system, logical processor acpi_id is required in _UID property
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* of DSDT table, so we should check device_declaration here
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*/
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if (device_declaration && (core_pic->processor_id == acpi_id)) {
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*phys_id = core_pic->core_id;
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return 0;
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}
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return -EINVAL;
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}
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static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt,
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int type, u32 acpi_id)
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{
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unsigned long madt_end, entry;
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phys_cpuid_t phys_id = PHYS_CPUID_INVALID; /* CPU hardware ID */
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if (!madt)
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return phys_id;
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entry = (unsigned long)madt;
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madt_end = entry + madt->header.length;
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/* Parse all entries looking for a match. */
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entry += sizeof(struct acpi_table_madt);
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while (entry + sizeof(struct acpi_subtable_header) < madt_end) {
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struct acpi_subtable_header *header =
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(struct acpi_subtable_header *)entry;
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if (header->type == ACPI_MADT_TYPE_LOCAL_APIC) {
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if (!map_lapic_id(header, acpi_id, &phys_id))
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break;
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} else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC) {
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if (!map_x2apic_id(header, type, acpi_id, &phys_id))
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break;
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} else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) {
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if (!map_lsapic_id(header, type, acpi_id, &phys_id))
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break;
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} else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) {
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if (!map_gicc_mpidr(header, type, acpi_id, &phys_id))
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break;
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} else if (header->type == ACPI_MADT_TYPE_RINTC) {
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if (!map_rintc_hartid(header, type, acpi_id, &phys_id))
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break;
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} else if (header->type == ACPI_MADT_TYPE_CORE_PIC) {
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if (!map_core_pic_id(header, type, acpi_id, &phys_id))
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break;
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}
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entry += header->length;
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}
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return phys_id;
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}
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phys_cpuid_t __init acpi_map_madt_entry(u32 acpi_id)
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{
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struct acpi_table_madt *madt = NULL;
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phys_cpuid_t rv;
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acpi_get_table(ACPI_SIG_MADT, 0,
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(struct acpi_table_header **)&madt);
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if (!madt)
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return PHYS_CPUID_INVALID;
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rv = map_madt_entry(madt, 1, acpi_id);
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acpi_put_table((struct acpi_table_header *)madt);
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return rv;
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}
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int __init acpi_get_madt_revision(void)
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{
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struct acpi_table_header *madt = NULL;
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int revision;
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if (ACPI_FAILURE(acpi_get_table(ACPI_SIG_MADT, 0, &madt)))
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return -EINVAL;
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revision = madt->revision;
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acpi_put_table(madt);
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return revision;
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}
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static phys_cpuid_t map_mat_entry(acpi_handle handle, int type, u32 acpi_id)
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{
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struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
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union acpi_object *obj;
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struct acpi_subtable_header *header;
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phys_cpuid_t phys_id = PHYS_CPUID_INVALID;
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if (ACPI_FAILURE(acpi_evaluate_object(handle, "_MAT", NULL, &buffer)))
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goto exit;
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if (!buffer.length || !buffer.pointer)
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goto exit;
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obj = buffer.pointer;
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if (obj->type != ACPI_TYPE_BUFFER ||
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obj->buffer.length < sizeof(struct acpi_subtable_header)) {
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goto exit;
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}
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header = (struct acpi_subtable_header *)obj->buffer.pointer;
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if (header->type == ACPI_MADT_TYPE_LOCAL_APIC)
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map_lapic_id(header, acpi_id, &phys_id);
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else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC)
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map_lsapic_id(header, type, acpi_id, &phys_id);
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else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC)
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map_x2apic_id(header, type, acpi_id, &phys_id);
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else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT)
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map_gicc_mpidr(header, type, acpi_id, &phys_id);
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else if (header->type == ACPI_MADT_TYPE_CORE_PIC)
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map_core_pic_id(header, type, acpi_id, &phys_id);
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exit:
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kfree(buffer.pointer);
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return phys_id;
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}
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phys_cpuid_t acpi_get_phys_id(acpi_handle handle, int type, u32 acpi_id)
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{
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phys_cpuid_t phys_id;
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phys_id = map_mat_entry(handle, type, acpi_id);
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if (invalid_phys_cpuid(phys_id))
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phys_id = map_madt_entry(get_madt_table(), type, acpi_id);
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return phys_id;
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}
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EXPORT_SYMBOL_GPL(acpi_get_phys_id);
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int acpi_map_cpuid(phys_cpuid_t phys_id, u32 acpi_id)
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{
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#ifdef CONFIG_SMP
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int i;
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#endif
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if (invalid_phys_cpuid(phys_id)) {
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/*
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* On UP processor, there is no _MAT or MADT table.
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* So above phys_id is always set to PHYS_CPUID_INVALID.
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*
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* BIOS may define multiple CPU handles even for UP processor.
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* For example,
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*
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* Scope (_PR)
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* {
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* Processor (CPU0, 0x00, 0x00000410, 0x06) {}
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* Processor (CPU1, 0x01, 0x00000410, 0x06) {}
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* Processor (CPU2, 0x02, 0x00000410, 0x06) {}
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* Processor (CPU3, 0x03, 0x00000410, 0x06) {}
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* }
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*
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* Ignores phys_id and always returns 0 for the processor
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* handle with acpi id 0 if nr_cpu_ids is 1.
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* This should be the case if SMP tables are not found.
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* Return -EINVAL for other CPU's handle.
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*/
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if (nr_cpu_ids <= 1 && acpi_id == 0)
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return acpi_id;
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else
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return -EINVAL;
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}
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#ifdef CONFIG_SMP
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for_each_possible_cpu(i) {
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if (cpu_physical_id(i) == phys_id)
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return i;
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}
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#else
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/* In UP kernel, only processor 0 is valid */
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if (phys_id == 0)
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return phys_id;
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#endif
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return -ENODEV;
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}
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int acpi_get_cpuid(acpi_handle handle, int type, u32 acpi_id)
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{
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phys_cpuid_t phys_id;
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phys_id = acpi_get_phys_id(handle, type, acpi_id);
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return acpi_map_cpuid(phys_id, acpi_id);
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}
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EXPORT_SYMBOL_GPL(acpi_get_cpuid);
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#ifdef CONFIG_ACPI_HOTPLUG_IOAPIC
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static int get_ioapic_id(struct acpi_subtable_header *entry, u32 gsi_base,
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u64 *phys_addr, int *ioapic_id)
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{
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struct acpi_madt_io_apic *ioapic = (struct acpi_madt_io_apic *)entry;
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if (ioapic->global_irq_base != gsi_base)
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return 0;
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*phys_addr = ioapic->address;
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*ioapic_id = ioapic->id;
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return 1;
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}
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static int parse_madt_ioapic_entry(u32 gsi_base, u64 *phys_addr)
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{
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struct acpi_subtable_header *hdr;
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unsigned long madt_end, entry;
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struct acpi_table_madt *madt;
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int apic_id = -1;
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madt = get_madt_table();
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if (!madt)
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return apic_id;
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entry = (unsigned long)madt;
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madt_end = entry + madt->header.length;
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/* Parse all entries looking for a match. */
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entry += sizeof(struct acpi_table_madt);
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while (entry + sizeof(struct acpi_subtable_header) < madt_end) {
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hdr = (struct acpi_subtable_header *)entry;
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if (hdr->type == ACPI_MADT_TYPE_IO_APIC &&
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get_ioapic_id(hdr, gsi_base, phys_addr, &apic_id))
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break;
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else
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entry += hdr->length;
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}
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return apic_id;
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}
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static int parse_mat_ioapic_entry(acpi_handle handle, u32 gsi_base,
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u64 *phys_addr)
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{
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struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
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struct acpi_subtable_header *header;
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union acpi_object *obj;
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int apic_id = -1;
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if (ACPI_FAILURE(acpi_evaluate_object(handle, "_MAT", NULL, &buffer)))
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goto exit;
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if (!buffer.length || !buffer.pointer)
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|
goto exit;
|
|
|
|
obj = buffer.pointer;
|
|
if (obj->type != ACPI_TYPE_BUFFER ||
|
|
obj->buffer.length < sizeof(struct acpi_subtable_header))
|
|
goto exit;
|
|
|
|
header = (struct acpi_subtable_header *)obj->buffer.pointer;
|
|
if (header->type == ACPI_MADT_TYPE_IO_APIC)
|
|
get_ioapic_id(header, gsi_base, phys_addr, &apic_id);
|
|
|
|
exit:
|
|
kfree(buffer.pointer);
|
|
return apic_id;
|
|
}
|
|
|
|
/**
|
|
* acpi_get_ioapic_id - Get IOAPIC ID and physical address matching @gsi_base
|
|
* @handle: ACPI object for IOAPIC device
|
|
* @gsi_base: GSI base to match with
|
|
* @phys_addr: Pointer to store physical address of matching IOAPIC record
|
|
*
|
|
* Walk resources returned by ACPI_MAT method, then ACPI MADT table, to search
|
|
* for an ACPI IOAPIC record matching @gsi_base.
|
|
* Return IOAPIC id and store physical address in @phys_addr if found a match,
|
|
* otherwise return <0.
|
|
*/
|
|
int acpi_get_ioapic_id(acpi_handle handle, u32 gsi_base, u64 *phys_addr)
|
|
{
|
|
int apic_id;
|
|
|
|
apic_id = parse_mat_ioapic_entry(handle, gsi_base, phys_addr);
|
|
if (apic_id == -1)
|
|
apic_id = parse_madt_ioapic_entry(gsi_base, phys_addr);
|
|
|
|
return apic_id;
|
|
}
|
|
#endif /* CONFIG_ACPI_HOTPLUG_IOAPIC */
|