45e981b86d
- Drop endpoint redundant masking of global IRQ events (Manivannan Sadhasivam) - Clarify unknown global IRQ message and only log it once to avoid a flood (Manivannan Sadhasivam) - Add Manivannan Sadhasivam as maintainer of qcom endpoint driver (Manivannan Sadhasivam) - Add 'linux,pci-domain' property to endpoint DT binding (Manivannan Sadhasivam) - Assign PCI domain number for endpoint controllers (Manivannan Sadhasivam) - Add 'qcom_pcie_ep' and the PCI domain number to IRQ names for endpoint controller (Manivannan Sadhasivam) - Add global SPI interrupt for PCIe link events to DT binding (Manivannan Sadhasivam) - Add global RC interrupt handler to handle 'Link up' events and automatically enumerate hot-added devices (Manivannan Sadhasivam) - Avoid mirroring of DBI and iATU register space so it doesn't overlap BAR MMIO space (Prudhvi Yarlagadda) - Enable controller resources like PHY only after PERST# is deasserted to partially avoid the problem that the endpoint SoC crashes when accessing things when Refclk is absent (Manivannan Sadhasivam) - Rename dw_pcie.link_gen to max_link_speed to avoid ambiguity (Manivannan Sadhasivam) - Cache maximum link speed value in dw_pcie.max_link_speed for use by vendor drivers (Manivannan Sadhasivam) - Add 16.0 GT/s equalization and RX lane margining settings (Shashank Babu Chinta Venkata) - Pass domain number to pci_bus_release_domain_nr() explicitly to avoid a NULL pointer dereference (Manivannan Sadhasivam) * pci/controller/qcom: PCI: Pass domain number to pci_bus_release_domain_nr() explicitly PCI: qcom: Add RX lane margining settings for 16.0 GT/s PCI: qcom: Add equalization settings for 16.0 GT/s PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed' PCI: qcom-ep: Enable controller resources like PHY only after refclk is available PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names PCI: endpoint: Assign PCI domain number for endpoint controllers dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property dt-bindings: PCI: pci-ep: Update Maintainers PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event PCI: qcom-ep: Drop the redundant masking of global IRQ events
104 lines
1.6 KiB
YAML
104 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm PCI Express Root Complex Common Properties
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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properties:
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reg:
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minItems: 4
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maxItems: 6
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reg-names:
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minItems: 4
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maxItems: 6
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interrupts:
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minItems: 1
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maxItems: 9
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interrupt-names:
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minItems: 1
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maxItems: 9
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iommu-map:
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minItems: 1
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maxItems: 16
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clocks:
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minItems: 3
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maxItems: 13
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clock-names:
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minItems: 3
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maxItems: 13
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dma-coherent: true
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: pcie-mem
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- const: cpu-pcie
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: pciephy
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power-domains:
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maxItems: 1
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required-opps:
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maxItems: 1
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resets:
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minItems: 1
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maxItems: 12
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reset-names:
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minItems: 1
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maxItems: 12
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perst-gpios:
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description: GPIO controlled connection to PERST# signal
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maxItems: 1
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wake-gpios:
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description: GPIO controlled connection to WAKE# signal
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maxItems: 1
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vddpe-3v3-supply:
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description: PCIe endpoint power supply
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required:
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- reg
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- reg-names
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- interrupt-map-mask
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- interrupt-map
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- clocks
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- clock-names
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anyOf:
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- required:
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- interrupts
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- interrupt-names
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- "#interrupt-cells"
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- required:
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- msi-map
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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additionalProperties: true
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