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linux/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
Matthew Gerlach b08929e1ec
dt-bindings: PCI: altera: Convert to YAML
Convert the devicetree bindings for the Altera Root Port PCIe controller
from text to YAML.

While at it, update the entries in the interrupt-map field to have the
correct number of address cells for the interrupt parent.

Link: https://lore.kernel.org/linux-pci/20240702162652.1349121-1-matthew.gerlach@linux.intel.com
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2024-09-04 15:22:38 +00:00

115 lines
2.5 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2015, 2019, 2024, Intel Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera PCIe Root Port
maintainers:
- Matthew Gerlach <matthew.gerlach@linux.intel.com>
properties:
compatible:
enum:
- altr,pcie-root-port-1.0
- altr,pcie-root-port-2.0
reg:
items:
- description: TX slave port region
- description: Control register access region
- description: Hard IP region
minItems: 2
reg-names:
items:
- const: Txs
- const: Cra
- const: Hip
minItems: 2
interrupts:
maxItems: 1
interrupt-controller: true
interrupt-map-mask:
items:
- const: 0
- const: 0
- const: 0
- const: 7
interrupt-map:
maxItems: 4
"#interrupt-cells":
const: 1
msi-parent: true
required:
- compatible
- reg
- reg-names
- interrupts
- "#interrupt-cells"
- interrupt-controller
- interrupt-map
- interrupt-map-mask
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
- if:
properties:
compatible:
enum:
- altr,pcie-root-port-1.0
then:
properties:
reg:
maxItems: 2
reg-names:
maxItems: 2
else:
properties:
reg:
minItems: 3
reg-names:
minItems: 3
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
pcie_0: pcie@c00000000 {
compatible = "altr,pcie-root-port-1.0";
reg = <0xc0000000 0x20000000>,
<0xff220000 0x00004000>;
reg-names = "Txs", "Cra";
interrupt-parent = <&hps_0_arm_gic_0>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
bus-range = <0x0 0xff>;
device_type = "pci";
msi-parent = <&msi_to_gic_gen_0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_0 0 0 0 1>,
<0 0 0 2 &pcie_0 0 0 0 2>,
<0 0 0 3 &pcie_0 0 0 0 3>,
<0 0 0 4 &pcie_0 0 0 0 4>;
ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000>,
<0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
};