c7de6ee3d3
Add two description for register space of rtic. There are two register
space, one is for control and status, the other optional space is
recoverable error indication register space.
Fix below CHECK_DTBS error:
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dtb: crypto@1700000: rtic@60000:reg: [[393216, 256], [396800, 24]] is too long
from schema $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
270 lines
7.7 KiB
YAML
270 lines
7.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale SEC 4
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maintainers:
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- '"Horia Geantă" <horia.geanta@nxp.com>'
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- Pankaj Gupta <pankaj.gupta@nxp.com>
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- Gaurav Jain <gaurav.jain@nxp.com>
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description: |
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NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
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Accelerator and Assurance Module (CAAM).
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SEC 4 h/w can process requests from 2 types of sources.
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1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
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2. Job Rings (HW interface between cores & SEC 4 registers).
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High Speed Data Path Configuration:
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HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
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such as the P4080. The number of simultaneous dequeues the QI can make is
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equal to the number of Descriptor Controller (DECO) engines in a particular
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SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
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dequeue from 5 subportals simultaneously.
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Job Ring Data Path Configuration:
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Each JR is located on a separate 4k page, they may (or may not) be made visible
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in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
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up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
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properties:
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compatible:
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oneOf:
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- items:
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- const: fsl,sec-v5.4
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- const: fsl,sec-v5.0
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- const: fsl,sec-v4.0
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- items:
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- enum:
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- fsl,imx6ul-caam
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- fsl,sec-v5.0
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- const: fsl,sec-v4.0
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- const: fsl,sec-v4.0
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reg:
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maxItems: 1
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ranges:
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maxItems: 1
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'#address-cells':
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enum: [1, 2]
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'#size-cells':
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enum: [1, 2]
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clocks:
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minItems: 1
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maxItems: 4
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clock-names:
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minItems: 1
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maxItems: 4
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items:
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enum: [mem, aclk, ipg, emi_slow]
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dma-coherent: true
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interrupts:
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maxItems: 1
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fsl,sec-era:
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description: Defines the 'ERA' of the SEC device.
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$ref: /schemas/types.yaml#/definitions/uint32
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patternProperties:
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'^jr@[0-9a-f]+$':
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type: object
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additionalProperties: false
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description:
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Job Ring (JR) Node. Defines data processing interface to SEC 4 across the
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peripheral bus for purposes of processing cryptographic descriptors. The
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specified address range can be made visible to one (or more) cores. The
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interrupt defined for this node is controlled within the address range of
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this node.
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properties:
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compatible:
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oneOf:
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- items:
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- const: fsl,sec-v5.4-job-ring
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- const: fsl,sec-v5.0-job-ring
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- const: fsl,sec-v4.0-job-ring
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- items:
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- const: fsl,sec-v5.0-job-ring
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- const: fsl,sec-v4.0-job-ring
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- const: fsl,sec-v4.0-job-ring
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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fsl,liodn:
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description:
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Specifies the LIODN to be used in conjunction with the ppid-to-liodn
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table that specifies the PPID to LIODN mapping. Needed if the PAMU is
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used. Value is a 12 bit value where value is a LIODN ID for this JR.
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This property is normally set by boot firmware.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 0xfff
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'^rtic@[0-9a-f]+$':
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type: object
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additionalProperties: false
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description:
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Run Time Integrity Check (RTIC) Node. Defines a register space that
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contains up to 5 sets of addresses and their lengths (sizes) that will be
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checked at run time. After an initial hash result is calculated, these
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addresses are checked by HW to monitor any change. If any memory is
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modified, a Security Violation is triggered (see SNVS definition).
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properties:
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compatible:
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oneOf:
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- items:
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- const: fsl,sec-v5.4-rtic
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- const: fsl,sec-v5.0-rtic
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- const: fsl,sec-v4.0-rtic
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- const: fsl,sec-v4.0-rtic
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reg:
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items:
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- description: RTIC control and status register space.
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- description: RTIC recoverable error indication register space.
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minItems: 1
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ranges:
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maxItems: 1
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interrupts:
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maxItems: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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patternProperties:
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'^rtic-[a-z]@[0-9a-f]+$':
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type: object
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additionalProperties: false
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description:
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Run Time Integrity Check (RTIC) Memory Node defines individual RTIC
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memory regions that are used to perform run-time integrity check of
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memory areas that should not modified. The node defines a register
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that contains the memory address & length (combined) and a second
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register that contains the hash result in big endian format.
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properties:
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compatible:
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oneOf:
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- items:
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- const: fsl,sec-v5.4-rtic-memory
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- const: fsl,sec-v5.0-rtic-memory
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- const: fsl,sec-v4.0-rtic-memory
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- const: fsl,sec-v4.0-rtic-memory
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reg:
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items:
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- description: RTIC memory address
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- description: RTIC hash result
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fsl,liodn:
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description:
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Specifies the LIODN to be used in conjunction with the
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ppid-to-liodn table that specifies the PPID to LIODN mapping.
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Needed if the PAMU is used. Value is a 12 bit value where value
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is a LIODN ID for this JR. This property is normally set by boot
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firmware.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 0xfff
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fsl,rtic-region:
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description:
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Specifies the HW address (36 bit address) for this region
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followed by the length of the HW partition to be checked;
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the address is represented as a 64 bit quantity followed
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by a 32 bit length.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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required:
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- compatible
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- reg
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- ranges
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additionalProperties: false
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examples:
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- |
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crypto@300000 {
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compatible = "fsl,sec-v4.0";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x300000 0x10000>;
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ranges = <0 0x300000 0x10000>;
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interrupts = <92 2>;
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jr@1000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x1000 0x1000>;
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interrupts = <88 2>;
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};
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jr@2000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x2000 0x1000>;
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interrupts = <89 2>;
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};
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jr@3000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x3000 0x1000>;
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interrupts = <90 2>;
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};
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jr@4000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x4000 0x1000>;
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interrupts = <91 2>;
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};
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rtic@6000 {
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compatible = "fsl,sec-v4.0-rtic";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x6000 0x100>;
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ranges = <0x0 0x6100 0xe00>;
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rtic-a@0 {
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compatible = "fsl,sec-v4.0-rtic-memory";
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reg = <0x00 0x20>, <0x100 0x80>;
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};
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rtic-b@20 {
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compatible = "fsl,sec-v4.0-rtic-memory";
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reg = <0x20 0x20>, <0x200 0x80>;
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};
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rtic-c@40 {
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compatible = "fsl,sec-v4.0-rtic-memory";
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reg = <0x40 0x20>, <0x300 0x80>;
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};
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rtic-d@60 {
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compatible = "fsl,sec-v4.0-rtic-memory";
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reg = <0x60 0x20>, <0x500 0x80>;
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};
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};
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};
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...
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