1
linux/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
Daniel Golle afd36e9d91 dt-bindings: clock: mediatek: add clock controllers of MT7988
Add various clock controllers found in the MT7988 SoC to existing
bindings (if applicable) and add files for the new ethwarp, mcusys
and xfi-pll clock controllers not previously present in any SoC.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:55:17 -08:00

49 lines
975 B
YAML

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT7988 XFI PLL Clock Controller
maintainers:
- Daniel Golle <daniel@makrotopia.org>
description:
The MediaTek XFI PLL controller provides the 156.25MHz clock for the
Ethernet SerDes PHY from the 40MHz top_xtal clock.
properties:
compatible:
const: mediatek,mt7988-xfi-pll
reg:
maxItems: 1
resets:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- resets
- '#clock-cells'
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
resets = <&watchdog 16>;
#clock-cells = <1>;
};
};