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dt-bindings: clock: mediatek: add clock controllers of MT7988

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Add various clock controllers found in the MT7988 SoC to existing
bindings (if applicable) and add files for the new ethwarp, mcusys
and xfi-pll clock controllers not previously present in any SoC.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Daniel Golle 2023-12-17 21:49:55 +00:00 committed by Stephen Boyd
parent 5cfa3beb77
commit afd36e9d91
7 changed files with 161 additions and 9 deletions
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1
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
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@ -30,6 +30,7 @@ properties:
- mediatek,mt7629-infracfg
- mediatek,mt7981-infracfg
- mediatek,mt7986-infracfg
- mediatek,mt7988-infracfg
- mediatek,mt8135-infracfg
- mediatek,mt8167-infracfg
- mediatek,mt8173-infracfg

1
Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
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@ -22,6 +22,7 @@ properties:
- mediatek,mt7622-apmixedsys
- mediatek,mt7981-apmixedsys
- mediatek,mt7986-apmixedsys
- mediatek,mt7988-apmixedsys
- mediatek,mt8135-apmixedsys
- mediatek,mt8173-apmixedsys
- mediatek,mt8516-apmixedsys

1
Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
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@ -22,6 +22,7 @@ properties:
- mediatek,mt7629-ethsys
- mediatek,mt7981-ethsys
- mediatek,mt7986-ethsys
- mediatek,mt7988-ethsys
- const: syscon
- items:
- const: mediatek,mt7623-ethsys

52
Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml Normal file
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@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT7988 ethwarp Controller
maintainers:
- Daniel Golle <daniel@makrotopia.org>
description:
The Mediatek MT7988 ethwarp controller provides clocks and resets for the
Ethernet related subsystems found the MT7988 SoC.
The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
properties:
compatible:
items:
- const: mediatek,mt7988-ethwarp
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/reset/ti-syscon.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@15031000 {
compatible = "mediatek,mt7988-ethwarp";
reg = <0 0x15031000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};

48
Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml Normal file
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@ -0,0 +1,48 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT7988 XFI PLL Clock Controller
maintainers:
- Daniel Golle <daniel@makrotopia.org>
description:
The MediaTek XFI PLL controller provides the 156.25MHz clock for the
Ethernet SerDes PHY from the 40MHz top_xtal clock.
properties:
compatible:
const: mediatek,mt7988-xfi-pll
reg:
maxItems: 1
resets:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- resets
- '#clock-cells'
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
resets = <&watchdog 16>;
#clock-cells = <1>;
};
};

2
Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
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@ -37,6 +37,8 @@ properties:
- mediatek,mt7629-topckgen
- mediatek,mt7981-topckgen
- mediatek,mt7986-topckgen
- mediatek,mt7988-mcusys
- mediatek,mt7988-topckgen
- mediatek,mt8167-topckgen
- mediatek,mt8183-topckgen
- const: syscon

65
Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
View File

@ -15,15 +15,22 @@ description:
properties:
compatible:
items:
- enum:
- mediatek,mt7622-sgmiisys
- mediatek,mt7629-sgmiisys
- mediatek,mt7981-sgmiisys_0
- mediatek,mt7981-sgmiisys_1
- mediatek,mt7986-sgmiisys_0
- mediatek,mt7986-sgmiisys_1
- const: syscon
oneOf:
- items:
- enum:
- mediatek,mt7622-sgmiisys
- mediatek,mt7629-sgmiisys
- mediatek,mt7981-sgmiisys_0
- mediatek,mt7981-sgmiisys_1
- mediatek,mt7986-sgmiisys_0
- mediatek,mt7986-sgmiisys_1
- const: syscon
- items:
- enum:
- mediatek,mt7988-sgmiisys0
- mediatek,mt7988-sgmiisys1
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
@ -35,11 +42,51 @@ properties:
description: Invert polarity of the SGMII data lanes
type: boolean
pcs:
type: object
description: MediaTek LynxI HSGMII PCS
properties:
compatible:
const: mediatek,mt7988-sgmii
clocks:
maxItems: 3
clock-names:
items:
- const: sgmii_sel
- const: sgmii_tx
- const: sgmii_rx
required:
- compatible
- clocks
- clock-names
additionalProperties: false
required:
- compatible
- reg
- '#clock-cells'
allOf:
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt7988-sgmiisys0
- mediatek,mt7988-sgmiisys1
then:
required:
- pcs
else:
properties:
pcs: false
additionalProperties: false
examples: