923a77a2e1
Add the S4 PLL clock controller dt-bindings in the S4 SoC family. Signed-off-by: Yu Tu <yu.tu@amlogic.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230904075504.23263-2-yu.tu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
50 lines
858 B
YAML
50 lines
858 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic S4 PLL Clock Controller
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maintainers:
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- Yu Tu <yu.tu@amlogic.com>
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properties:
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compatible:
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const: amlogic,s4-pll-clkc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: xtal
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"#clock-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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clkc_pll: clock-controller@fe008000 {
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compatible = "amlogic,s4-pll-clkc";
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reg = <0xfe008000 0x1e8>;
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clocks = <&xtal>;
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clock-names = "xtal";
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#clock-cells = <1>;
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};
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...
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