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dt-bindings: clock: document Amlogic S4 SoC PLL clock controller

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Add the S4 PLL clock controller dt-bindings in the S4 SoC family.

Signed-off-by: Yu Tu <yu.tu@amlogic.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230904075504.23263-2-yu.tu@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Yu Tu 2023-09-04 15:55:01 +08:00 committed by Jerome Brunet
parent 0bb80ecc33
commit 923a77a2e1
2 changed files with 92 additions and 0 deletions
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49
Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic S4 PLL Clock Controller
maintainers:
- Yu Tu <yu.tu@amlogic.com>
properties:
compatible:
const: amlogic,s4-pll-clkc
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: xtal
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
additionalProperties: false
examples:
- |
clkc_pll: clock-controller@fe008000 {
compatible = "amlogic,s4-pll-clkc";
reg = <0xfe008000 0x1e8>;
clocks = <&xtal>;
clock-names = "xtal";
#clock-cells = <1>;
};
...

43
include/dt-bindings/clock/amlogic,s4-pll-clkc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved.
* Author: Yu Tu <yu.tu@amlogic.com>
*/
#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
#define CLKID_FIXED_PLL_DCO 0
#define CLKID_FIXED_PLL 1
#define CLKID_FCLK_DIV2_DIV 2
#define CLKID_FCLK_DIV2 3
#define CLKID_FCLK_DIV3_DIV 4
#define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4_DIV 6
#define CLKID_FCLK_DIV4 7
#define CLKID_FCLK_DIV5_DIV 8
#define CLKID_FCLK_DIV5 9
#define CLKID_FCLK_DIV7_DIV 10
#define CLKID_FCLK_DIV7 11
#define CLKID_FCLK_DIV2P5_DIV 12
#define CLKID_FCLK_DIV2P5 13
#define CLKID_GP0_PLL_DCO 14
#define CLKID_GP0_PLL 15
#define CLKID_HIFI_PLL_DCO 16
#define CLKID_HIFI_PLL 17
#define CLKID_HDMI_PLL_DCO 18
#define CLKID_HDMI_PLL_OD 19
#define CLKID_HDMI_PLL 20
#define CLKID_MPLL_50M_DIV 21
#define CLKID_MPLL_50M 22
#define CLKID_MPLL_PREDIV 23
#define CLKID_MPLL0_DIV 24
#define CLKID_MPLL0 25
#define CLKID_MPLL1_DIV 26
#define CLKID_MPLL1 27
#define CLKID_MPLL2_DIV 28
#define CLKID_MPLL2 29
#define CLKID_MPLL3_DIV 30
#define CLKID_MPLL3 31
#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H */