96f3b97873
The 'syspll' PLL is a general-purpose PLL designed specifically for the CPU clock. It is capable of producing output frequencies within the range of 768MHz to 1536MHz. The 'syspll_in' source clock is an optional parent connection from the peripherals clock controller. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240515185103.20256-3-ddrokosov@salutedevices.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
65 lines
1.5 KiB
YAML
65 lines
1.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic A1 PLL Clock Control Unit
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Jerome Brunet <jbrunet@baylibre.com>
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- Jian Hu <jian.hu@jian.hu.com>
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- Dmitry Rokosov <ddrokosov@sberdevices.ru>
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properties:
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compatible:
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const: amlogic,a1-pll-clkc
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'#clock-cells':
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const: 1
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reg:
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maxItems: 1
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clocks:
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items:
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- description: input fixpll_in
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- description: input hifipll_in
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- description: input syspll_in
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minItems: 2 # syspll_in is optional
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clock-names:
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items:
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- const: fixpll_in
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- const: hifipll_in
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- const: syspll_in
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minItems: 2 # syspll_in is optional
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required:
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- compatible
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- '#clock-cells'
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- reg
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
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apb {
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#address-cells = <2>;
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#size-cells = <2>;
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clock-controller@7c80 {
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compatible = "amlogic,a1-pll-clkc";
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reg = <0 0x7c80 0 0x18c>;
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#clock-cells = <1>;
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clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
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<&clkc_periphs CLKID_HIFIPLL_IN>,
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<&clkc_periphs CLKID_SYSPLL_IN>;
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clock-names = "fixpll_in", "hifipll_in", "syspll_in";
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};
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};
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