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Commit Graph

91 Commits

Author SHA1 Message Date
Mark Brown
f10d52087c
spi: Merge up fixes
A patch for Qualcomm depends on some fixes.
2024-09-12 12:38:44 +01:00
Krzysztof Kozlowski
6a2ab229ab
spi: cadence-quadspi: Simplify with scoped for each OF child loop
Use scoped for_each_available_child_of_node_scoped() when iterating over
device nodes to make code a bit simpler.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20240814143805.98874-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-08-14 18:26:51 +01:00
Vignesh Raghavendra
57d5af2660
spi: spi-cadence-quadspi: Fix OSPI NOR failures during system resume
Its necessary to call pm_runtime_force_*() hooks as part of system
suspend/resume calls so that the runtime_pm hooks get called. This
ensures latest state of the IP is cached and restored during system
sleep. This is especially true if runtime autosuspend is enabled as
runtime suspend hooks may not be called at all before system sleeps.

Without this patch, OSPI NOR enumeration (READ_ID) fails during resume
as context saved during suspend path is inconsistent.

Fixes: 078d62de43 ("spi: cadence-qspi: add system-wide suspend and resume callbacks")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://patch.msgid.link/20240814151237.3856184-1-vigneshr@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-08-14 18:26:29 +01:00
Théo Lebrun
47766799f5
spi: cadence-qspi: add mobileye,eyeq5-ospi compatible
Declare a new mobileye,eyeq5-ospi compatible.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20240423-cdns-qspi-mbly-v4-4-3d2a7b535ad0@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-26 11:09:25 +09:00
Théo Lebrun
c188739637
spi: cadence-qspi: add early busywait to cqspi_wait_for_bit()
Call readl_relaxed_poll_timeout() with no sleep at the start of
cqspi_wait_for_bit(). If its short timeout expires, a sleeping
readl_relaxed_poll_timeout() call takes the relay.

The reason is to avoid hrtimer interrupts on the system. All read
operations are expected to take less than 100µs.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20240423-cdns-qspi-mbly-v4-3-3d2a7b535ad0@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-26 11:09:24 +09:00
Théo Lebrun
1f257b92e6
spi: cadence-qspi: add no-IRQ mode to indirect reads
Support reads through polling, without any IRQ. The main reason is
performance; profiling shows that the first IRQ comes quickly on our
specific hardware. Once this IRQ arrives, we poll until all data is
retrieved. Avoid initial sleep to reduce IRQ count.

Hide this behavior behind a quirk flag.

This is confirmed through micro-benchmarks, but also end-to-end
performance tests. Mobileye EyeQ5, octal flash, reading 235M on a UBIFS
filesystem:
 - No optimizations, ~10.34s, ~22.7 MB/s, 199230 IRQs
 - CQSPI_SLOW_SRAM,  ~10.34s, ~22.7 MB/s,  70284 IRQs
 - CQSPI_RD_NO_IRQ,   ~9.37s, ~25.1 MB/s,    521 IRQs

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20240423-cdns-qspi-mbly-v4-2-3d2a7b535ad0@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-26 11:09:23 +09:00
Théo Lebrun
3bf64a2b66
spi: cadence-qspi: allow FIFO depth detection
If FIFO depth DT property is provided, check it matches what hardware
reports and warn otherwise. Else, use hardware provided value.

Hardware exposes FIFO depth indirectly because
CQSPI_REG_SRAMPARTITION is partially read-only.

Move probe cqspi->ddata assignment prior to cqspi_of_get_pdata() call.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20240423-cdns-qspi-mbly-v4-1-3d2a7b535ad0@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-26 11:09:22 +09:00
Théo Lebrun
563f8598cb
spi: cadence-qspi: minimise register accesses on each op if !DTR
cqspi_enable_dtr() is called for each operation, commands or not, reads
or writes. It writes CQSPI_REG_CONFIG then waits for idle (three
successful reads). Skip that in the no-DTR case if DTR is already
disabled.

It cannot be skipped in the DTR case as cqspi_setup_opcode_ext() writes
to a register and we must wait for idle state.

According to ftrace, the average cqspi_exec_mem_op() call goes from
85.4µs to 83.6µs when reading 235M over UBIFS on an octal flash.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://msgid.link/r/20240405-cdns-qspi-mbly-v2-6-956679866d6d@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-08 15:18:10 +01:00
Théo Lebrun
dcc594aef1
spi: cadence-qspi: store device data pointer in private struct
Avoid of_device_get_match_data() call on each IRQ and each read
operation. Store pointer in `struct cqspi_st` device instance.

End-to-end performance measurements improve with this patch. On a given
octal flash, reading 235M over UBIFS is ~3.4% faster. During that read,
the average cqspi_exec_mem_op() call goes from 85.4µs to 80.7µs
according to ftrace. The worst case goes from 622.4µs to 615.2µs.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://msgid.link/r/20240405-cdns-qspi-mbly-v2-4-956679866d6d@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-08 15:18:09 +01:00
Linus Torvalds
6cdebf62a1 spi: Updates for v6.9
This release sees some exciting changes from David Lechner which
 implements some optimisations that have been talked about for a long
 time which allows client drivers to pre-prepare SPI messages for
 repeated or low latency use.  This lets us move work out of latency
 sensitive paths and avoid repeating work for frequently performed
 operations.  As well as being useful in itself this will also be used in
 future to allow controllers to directly trigger SPI operations (eg, from
 interrupts).
 
 Otherwise this release has mostly been focused on cleanups, plus a
 couple of new devices:
 
  - Support for pre-optimising messages.
  - A big set of updates from Uwe Kleine-König moving drivers to use APIs
    with more modern terminology for controllers.
  - Major overhaul of the s3c64xx driver.
  - Support for Google GS101 and Samsung Exynos850.
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Merge tag 'spi-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
 "This release sees some exciting changes from David Lechner which
  implements some optimisations that have been talked about for a long
  time which allows client drivers to pre-prepare SPI messages for
  repeated or low latency use. This lets us move work out of latency
  sensitive paths and avoid repeating work for frequently performed
  operations. As well as being useful in itself this will also be used
  in future to allow controllers to directly trigger SPI operations (eg,
  from interrupts).

  Otherwise this release has mostly been focused on cleanups, plus a
  couple of new devices:

   - Support for pre-optimising messages

   - A big set of updates from Uwe Kleine-König moving drivers to use
     APIs with more modern terminology for controllers

   - Major overhaul of the s3c64xx driver

   - Support for Google GS101 and Samsung Exynos850"

* tag 'spi-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (122 commits)
  spi: Introduce SPI_INVALID_CS and is_valid_cs()
  spi: Fix types of the last chip select storage variables
  spi: Consistently use BIT for cs_index_mask
  spi: Exctract spi_dev_check_cs() helper
  spi: Exctract spi_set_all_cs_unused() helper
  spi: s3c64xx: switch exynos850 to new port config data
  spi: s3c64xx: switch gs101 to new port config data
  spi: s3c64xx: deprecate fifo_lvl_mask, rx_lvl_offset and port_id
  spi: s3c64xx: get rid of the OF alias ID dependency
  spi: s3c64xx: introduce s3c64xx_spi_set_port_id()
  spi: s3c64xx: let the SPI core determine the bus number
  spi: s3c64xx: allow FIFO depth to be determined from the compatible
  spi: s3c64xx: retrieve the FIFO depth from the device tree
  spi: s3c64xx: determine the fifo depth only once
  spi: s3c64xx: allow full FIFO masks
  spi: s3c64xx: define a magic value
  spi: dt-bindings: introduce FIFO depth properties
  spi: axi-spi-engine: use struct_size() macro
  spi: axi-spi-engine: use __counted_by() attribute
  spi: axi-spi-engine: remove p from struct spi_engine_message_state
  ...
2024-03-13 11:07:37 -07:00
Théo Lebrun
078d62de43
spi: cadence-qspi: add system-wide suspend and resume callbacks
Each SPI controller is expected to call the spi_controller_suspend() and
spi_controller_resume() callbacks at system-wide suspend and resume.

It (1) handles the kthread worker for queued controllers and (2) marks
the controller as suspended to have spi_sync() fail while the
controller is unavailable.

Those two operations do not require the controller to be active, we do
not need to increment the runtime PM usage counter.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://msgid.link/r/20240222-cdns-qspi-pm-fix-v4-4-6b6af8bcbf59@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-22 12:25:10 +00:00
Théo Lebrun
4efa1250b5
spi: cadence-qspi: put runtime in runtime PM hooks names
Follow kernel naming convention with regards to power-management
callback function names.

The convention in the kernel is:
 - prefix_suspend means the system-wide suspend callback;
 - prefix_runtime_suspend means the runtime PM suspend callback.
The same applies to resume callbacks.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://msgid.link/r/20240222-cdns-qspi-pm-fix-v4-3-6b6af8bcbf59@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-22 12:25:09 +00:00
Théo Lebrun
959043afe5
spi: cadence-qspi: remove system-wide suspend helper calls from runtime PM hooks
The ->runtime_suspend() and ->runtime_resume() callbacks are not
expected to call spi_controller_suspend() and spi_controller_resume().
Remove calls to those in the cadence-qspi driver.

Those helpers have two roles currently:
 - They stop/start the queue, including dealing with the kworker.
 - They toggle the SPI controller SPI_CONTROLLER_SUSPENDED flag. It
   requires acquiring ctlr->bus_lock_mutex.

Step one is irrelevant because cadence-qspi is not queued. Step two
however has two implications:
 - A deadlock occurs, because ->runtime_resume() is called in a context
   where the lock is already taken (in the ->exec_op() callback, where
   the usage count is incremented).
 - It would disallow all operations once the device is auto-suspended.

Here is a brief call tree highlighting the mutex deadlock:

spi_mem_exec_op()
        ...
        spi_mem_access_start()
                mutex_lock(&ctlr->bus_lock_mutex)

        cqspi_exec_mem_op()
                pm_runtime_resume_and_get()
                        cqspi_resume()
                                spi_controller_resume()
                                        mutex_lock(&ctlr->bus_lock_mutex)
                ...

        spi_mem_access_end()
                mutex_unlock(&ctlr->bus_lock_mutex)
        ...

Fixes: 0578a6dbfe ("spi: spi-cadence-quadspi: add runtime pm support")
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://msgid.link/r/20240222-cdns-qspi-pm-fix-v4-2-6b6af8bcbf59@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-22 12:25:08 +00:00
Théo Lebrun
32ce3bb57b
spi: cadence-qspi: fix pointer reference in runtime PM hooks
dev_get_drvdata() gets used to acquire the pointer to cqspi and the SPI
controller. Neither embed the other; this lead to memory corruption.

On a given platform (Mobileye EyeQ5) the memory corruption is hidden
inside cqspi->f_pdata. Also, this uninitialised memory is used as a
mutex (ctlr->bus_lock_mutex) by spi_controller_suspend().

Fixes: 2087e85bb6 ("spi: cadence-quadspi: fix suspend-resume implementations")
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://msgid.link/r/20240222-cdns-qspi-pm-fix-v4-1-6b6af8bcbf59@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-22 12:25:07 +00:00
Théo Lebrun
0f3841a5e1
spi: cadence-qspi: report correct number of chip-select
Set the ->num_chipselect field in struct cqspi_st and struct
spi_controller to the current number of chip-select. The value is
dependent on declared flashes in devicetree.

Previously, the num-cs property from devicetree or the maximum value was
being reported.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://msgid.link/r/20240209-cdns-qspi-cs-v1-3-a4f9dfed9ab4@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-21 16:27:20 +00:00
Théo Lebrun
7cc3522aed
spi: cadence-qspi: set maximum chip-select to 4
Change the maximum chip-select count in cadence-qspi to 4 instead of 16.
The value gets used as default ->num_chipselect when the num-cs DT
property isn't received from devicetree. It also determines the
cqspi->f_pdata array size.

Hardware only supports values up to 4; see cqspi_chipselect() that sets
CS using a one-bit-per-CS 4-bit register field.

Add a static_assert() call as a defensive measure to ensure we stay
under the SPI subsystem limit. It got set to 4 when introduced in
4d8ff6b099 ("spi: Add multi-cs memories support in SPI core") and
later increased to 16 in 2f8c7c3715 ("spi: Raise limit on number of
chip selects").

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://msgid.link/r/20240209-cdns-qspi-cs-v1-2-a4f9dfed9ab4@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-21 16:27:19 +00:00
Théo Lebrun
0d62c64a8e
spi: cadence-qspi: assert each subnode flash CS is valid
Check each flash CS against the num-cs property from devicetree.
Fallback to the driver max supported value (CQSPI_MAX_CHIPSELECT) if
num-cs isn't present.

cqspi->num_chipselect is set in cqspi_of_get_pdata() to the num-cs
devicetree property, or to CQSPI_MAX_CHIPSELECT if num-cs is not set.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://msgid.link/r/20240209-cdns-qspi-cs-v1-1-a4f9dfed9ab4@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-21 16:27:18 +00:00
Uwe Kleine-König
28e59d8bf1
spi: cadence-quadspi: Follow renaming of SPI "master" to "controller"
In commit 8caab75fd2 ("spi: Generalize SPI "master" to "controller"")
some functions and struct members were renamed. To not break all drivers
compatibility macros were provided.

To be able to remove these compatibility macros push the renaming into
this driver.

Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/d741960846b7f4896eeff91a4c8c7dfa8a6f8b7b.1707324794.git.u.kleine-koenig@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-08 11:54:49 +00:00
Uwe Kleine-König
e71011dacc
spi: cadence-quadspi: Don't emit error message on allocation error
Drivers are not supposed to emit an error message when a memory
allocation fails, as the kernel is very loud in this case already
anyhow.

Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/8da90785395664bf17d16428f46e84b95ef5cc3b.1707324794.git.u.kleine-koenig@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
2024-02-08 11:54:48 +00:00
Yang Yingliang
5cb475174c
spi: cadence-quadspi: add missing clk_disable_unprepare() in cqspi_probe()
cqspi_jh7110_clk_init() is called after clk_prepare_enable(cqspi->clk),
if it fails, it should goto label 'probe_reset_failed' to disable
cqspi->clk.

In the error path after calling cqspi_jh7110_clk_init(),
cqspi_jh7110_disable_clk() need be called.

Fixes: 33f1ef6d4e ("spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20231129081147.628004-1-yangyingliang@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-12-04 12:38:39 +00:00
Dhruva Gole
86401132d7
spi: spi-cadence-quadspi: Fix missing unwind goto warnings
The following smatch warnings [0] were recently introduced:

drivers/spi/spi-cadence-quadspi.c:1882 cqspi_probe() warn: missing
unwind goto?

Fix these warnings by releasing dma channel and adding a goto fail probe.

[0] https://lore.kernel.org/all/5e21c351-cd08-443e-8509-aecf242a4da9@kadam.mountain/

Fixes: 0578a6dbfe ("spi: spi-cadence-quadspi: add runtime pm support")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Closes: https://lore.kernel.org/r/202309140543.03dMbMM5-lkp@intel.com/
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230919074658.41666-1-d-gole@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-26 14:49:24 +02:00
Dhruva Gole
0578a6dbfe
spi: spi-cadence-quadspi: add runtime pm support
Add runtime pm support to cadence-qspi driver, this allows the driver to
suspend whenever it's is not actively being used thus reducing active
power consumed by the system.

Also, with the use of devm_pm_runtime_enable we no longer need the
fallback probe_pm_failed that used to pm_runtime_disable

Co-developed-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230829062706.786637-1-d-gole@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-11 01:32:21 +01:00
Yang Yingliang
1c75d749b5
spi: cadence-quadspi: switch to use modern name
Change legacy name master to modern name host or controller.

No functional changed.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20230807140717.3484180-11-yangyingliang@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-08-07 18:37:53 +01:00
William Qiu
33f1ef6d4e
spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
Add JH7110's clock initialization code to the driver.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Link: https://lore.kernel.org/r/20230804020254.291239-3-william.qiu@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-08-04 13:29:50 +01:00
Rob Herring
749396cb29
spi: Explicitly include correct DT includes
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230714174955.4064174-1-robh@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-14 20:53:00 +01:00
Linus Torvalds
84fccbba93 spi: Updates for v6.5
One small core feature this time around but mostly driver improvements
 and additions for SPI:
 
  - Add support for controlling the idle state of MOSI, some systems can
    support this and depending on the system integration may need it to
    avoid glitching in some situations.
  - Support for polling mode in the S3C64xx driver and DMA on the
    Qualcomm QSPI driver.
  - Support for several Allwinner SoCs, AMD Pensando Elba, Intel Mount
    Evans, Renesas RZ/V2M, and ST STM32H7.
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Merge tag 'spi-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
 "One small core feature this time around but mostly driver improvements
  and additions for SPI:

   - Add support for controlling the idle state of MOSI, some systems
     can support this and depending on the system integration may need
     it to avoid glitching in some situations

   - Support for polling mode in the S3C64xx driver and DMA on the
     Qualcomm QSPI driver

   - Support for several Allwinner SoCs, AMD Pensando Elba, Intel Mount
     Evans, Renesas RZ/V2M, and ST STM32H7"

* tag 'spi-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (66 commits)
  spi: dt-bindings: atmel,at91rm9200-spi: fix broken sam9x7 compatible
  spi: dt-bindings: atmel,at91rm9200-spi: add sam9x7 compatible
  spi: Add support for Renesas CSI
  spi: dt-bindings: Add bindings for RZ/V2M CSI
  spi: sun6i: Use the new helper to derive the xfer timeout value
  spi: atmel: Prevent false timeouts on long transfers
  spi: dt-bindings: stm32: do not disable spi-slave property for stm32f4-f7
  spi: Create a helper to derive adaptive timeouts
  spi: spi-geni-qcom: correctly handle -EPROBE_DEFER from dma_request_chan()
  spi: stm32: disable spi-slave property for stm32f4-f7
  spi: stm32: introduction of stm32h7 SPI device mode support
  spi: stm32: use dmaengine_terminate_{a}sync instead of _all
  spi: stm32: renaming of spi_master into spi_controller
  spi: dw: Remove misleading comment for Mount Evans SoC
  spi: dt-bindings: snps,dw-apb-ssi: Add compatible for Intel Mount Evans SoC
  spi: dw: Add compatible for Intel Mount Evans SoC
  spi: s3c64xx: Use dev_err_probe()
  spi: s3c64xx: Use the managed spi master allocation function
  spi: spl022: Probe defer is no error
  spi: spi-imx: fix mixing of native and gpio chipselects for imx51/imx53/imx6 variants
  ...
2023-06-28 13:48:42 -07:00
Jiasheng Jiang
947c70a213
spi: cadence-quadspi: Add missing check for dma_set_mask
Add check for dma_set_mask() and return the error if it fails.

Fixes: 1a6f854f7d ("spi: cadence-quadspi: Add Xilinx Versal external DMA support")
Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
Link: https://lore.kernel.org/r/20230606093859.27818-1-jiasheng@iscas.ac.cn
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-06 13:52:41 +01:00
Brad Larson
f5c2f9f958
spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC
The AMD Pensando Elba SoC has the Cadence QSPI controller integrated.

The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled
a dummy readback from the controller is performed to ensure
synchronization.

Signed-off-by: Brad Larson <blarson@amd.com
Link: https://lore.kernel.org/r/20230515181606.65953-8-blarson@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org
2023-05-17 10:38:57 +09:00
Dhruva Gole
be3206e890
spi: cadence-quadspi: use macro DEFINE_SIMPLE_DEV_PM_OPS
Using this macro makes the code more readable.
It also inits the members of dev_pm_ops in the following manner
without us explicitly needing to:

.suspend = cqspi_suspend, \
.resume = cqspi_resume, \
.freeze = cqspi_suspend, \
.thaw = cqspi_resume, \
.poweroff = cqspi_suspend, \
.restore = cqspi_resume

Also get rid of conditional compilation based on CONFIG_PM_SLEEP because
it introduces build issues with certain configs when CQSPI_DEV_PM_OPS is
just NULL.

Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/oe-kbuild-all/202304191900.2fARFQW9-lkp@intel.com/
Fixes: 1406234105 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230420054257.925092-1-d-gole@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-20 12:52:07 +01:00
Dhruva Gole
2087e85bb6
spi: cadence-quadspi: fix suspend-resume implementations
The cadence QSPI driver misbehaves after performing a full system suspend
resume:
...
spi-nor spi0.0: resume() failed
...
This results in a flash connected via OSPI interface after system suspend-
resume to be unusable.
fix these suspend and resume functions.

Fixes: 1406234105 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230417091027.966146-3-d-gole@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-18 14:02:35 +01:00
Sai Krishna Potthuri
c0b53f4e54
spi: cadence-quadspi: Disable the SPI before reconfiguring
Observed random DMA timeout failures while doing back to back
transfers which involves switching the modes from DMA to NON-DMA.
This issue is observed while testing the OSPI+UBIFS file system test case
where rootfs is mounted from OSPI UBIFS partition.
To avoid this issue, disable the SPI before changing the configuration
from external DMA to NON-DMA and vice versa and reenable it after changing
the configuration.
As per the Cadence Octal SPI design specification, it is recommended to
disable the Octal-SPI enable bit before reconfiguring.

Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Link: https://lore.kernel.org/r/20230320095931.2651714-3-sai.krishna.potthuri@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-17 18:16:39 +01:00
Sai Krishna Potthuri
22c8ce0aa2
spi: cadence-quadspi: Update the read timeout based on the length
When performing indirect read via external DMA the timeout for
completion is set equal to the read length instead of fixed timeout value.
For reads larger than 500 bytes, the timeout will continue to be
equal to the read length whereas for a small read like the Read Status
Register command, the timeout would be 1 or 2 milliseconds. This is not
enough to cover the overhead needed in setting up DMA, in that case make
sure the timeout is at least 500ms to allow DMA to finish. This solution
is inline with the timeout used for Direct read via DMA.

Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Link: https://lore.kernel.org/r/20230320095931.2651714-2-sai.krishna.potthuri@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-17 18:16:38 +01:00
Amit Kumar Mahapatra via Alsa-devel
9e264f3f85
spi: Replace all spi->chip_select and spi->cs_gpiod references with function call
Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod
members of struct spi_device to be an array. But changing the type of these
members to array would break the spi driver functionality. To make the
transition smoother introduced four new APIs to get/set the
spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and
spi->cs_gpiod references with get or set API calls.
While adding multi-cs support in further patches the chip_select & cs_gpiod
members of the spi_device structure would be converted to arrays & the
"idx" parameter of the APIs would be used as array index i.e.,
spi->chip_select[idx] & spi->cs_gpiod[idx] respectively.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Acked-by: Heiko Stuebner <heiko@sntech.de> # Rockchip drivers
Reviewed-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org> # Aspeed driver
Reviewed-by: Dhruva Gole <d-gole@ti.com> # SPI Cadence QSPI
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> # spi-stm32-qspi
Acked-by: William Zhang <william.zhang@broadcom.com> # bcm63xx-hsspi driver
Reviewed-by: Serge Semin <fancer.lancer@gmail.com> # DW SSI part
Link: https://lore.kernel.org/r/167847070432.26.15076794204368669839@mailman-core.alsa-project.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-03-11 12:34:01 +00:00
Mark Brown
2289fa0704
spi: Convert to platform remove callback returning
Merge series from Uwe Kleine-König <u.kleine-koenig@pengutronix.de>:

This patch series adapts the platform drivers below drivers/spi
to use the .remove_new() callback. Compared to the traditional .remove()
callback .remove_new() returns no value. This is a good thing because
the driver core doesn't (and cannot) cope for errors during remove. The
only effect of a non-zero return value in .remove() is that the driver
core emits a warning. The device is removed anyhow and an early return
from .remove() usually yields a resource leak.

By changing the remove callback to return void driver authors cannot
reasonably assume any more that there is some kind of cleanup later.

All drivers touched here returned zero unconditionally in their remove
callback, so they could all be converted trivially to .remove_new().
2023-03-07 16:46:18 +00:00
Uwe Kleine-König
6fe41879e9
spi: cadence-quadspi: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230303172041.2103336-16-u.kleine-koenig@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-03-06 12:31:16 +00:00
William Qiu
47fef94afe
spi: cadence-quadspi: Add support for StarFive JH7110 QSPI
Add QSPI reset operation in device probe and add RISCV support to
QUAD SPI Kconfig.

Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Link: https://lore.kernel.org/r/20230302105221.197421-3-william.qiu@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-03-05 23:38:58 +00:00
Hongbin Ji
152ac60677
spi: cadence-quadspi: Fix cancel the indirect read mask
This is to cancel the indirect read transfer process,
so should be use CQSPI_REG_INDIRECTRD_CANCEL_MASK

Signed-off-by: Hongbin Ji <jhb_ee@163.com>
Link: https://lore.kernel.org/r/20230222092128.4237-1-jhb_ee@163.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-23 11:40:16 +00:00
Dhruva Gole
d403fb6e76
spi: cadence-quadspi: use STIG mode for small reads
Fix the issue where some flash chips like cypress S25HS256T return the
value of the same register over and over in DAC mode.

For example in the TI K3-AM62x Processors refer [0] Technical Reference
Manual there is a layer of digital logic in front of the QSPI/OSPI
Drive when used in DAC mode. This is part of the Flash Subsystem (FSS)
which provides access to external Flash devices.

The FSS0_0_SYSCONFIG Register (Offset = 4h) has a BIT Field for
OSPI_32B_DISABLE_MODE which has a Reset value = 0. This means, OSPI 32bit
mode enabled by default.

Thus, by default controller operates in 32 bit mode causing it to always
align all data to 4 bytes from a 4byte aligned address. In some flash
chips like cypress for example if we try to read some regs in DAC mode
then it keeps sending the value of the first register that was requested
and inorder to read the next reg, we have to stop and re-initiate a new
transaction.

This causes wrong register values to be read than what is desired when
registers are read in DAC mode. Hence if the data.nbytes is very less
then prefer STIG mode for such small reads.

[0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf

Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230125081023.1573712-5-d-gole@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-14 13:25:26 +00:00
Dhruva Gole
a8674ae02d
spi: cadence-quadspi: setup ADDR Bits in cmd reads
Setup the Addr bit field while issuing register reads in STIG mode. This
is needed for example flashes like cypress define in their transaction
table that to read any register there is 1 cmd byte and a few more address
bytes trailing the cmd byte. Absence of addr bytes will obviously fail
to read correct data from flash register that maybe requested by flash
driver because the controller doesn't even specify which address of the
flash register the read is being requested from.

Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230125081023.1573712-4-d-gole@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-14 13:25:25 +00:00
Dhruva Gole
e8c51b1643
spi: cadence-quadspi: Add flag for direct mode writes
Create new flag inorder to avoid playing with use_direct_mode
flag currently being used throughout the driver.
Disable DAC write if auto polling is disabled or CQSPI_DISABLE_DAC_MODE
is set.

Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230125081023.1573712-3-d-gole@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-14 13:25:24 +00:00
Dhruva Gole
d4f43a2d05
spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion
If one leaves the CQSPI_REG_CMDCTRL in an unclean state this may cause
issues in future command reads. This issue came to light when some flash
reads in STIG mode were coming back dirty.

Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230125081023.1573712-2-d-gole@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-14 13:25:24 +00:00
Nathan Barrett-Morrison
f8fc65e50a
spi: cadence-quadspi: Add minimum operable clock rate warning to baudrate divisor calculation
This Cadence QSPI IP has a 4-bit clock divisor field
for baud rate division.  For example:

0b0000 = /2
0b0001 = /4
0b0010 = /6
...
0b1111 = /32

The maximum divisor is 32
(when div = CQSPI_REG_CONFIG_BAUD_MASK).

If we assume a reference clock of 500MHz and we set
our spi-max-frequency to something low, such as 10 MHz.
The calculated bit field for the divisor ends up being:

DIV_ROUND_UP(500000000/(2*10000000))-1 = 25

25 is 0b11001... which truncates to a divisor field of 0b1001 (or /20).

This is higher than our anticipated max-frequency of 10MHz
(500MHz/20 = 25 MHz).  Instead, let's make sure we're always using
the maximum divisor (/32) in this case and give the user a warning about
the rate adjustment.

Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Link: https://lore.kernel.org/r/20221128164147.158441-1-nathan.morrison@timesys.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-11-29 18:45:32 +00:00
Yang Yingliang
4e12ef2b2e
spi: cadence-quadspi: Use devm_platform_{get_and_}ioremap_resource()
Use the devm_platform_{get_and}_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource() separately.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20220928145852.1882221-2-yangyingliang@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-17 12:49:50 +01:00
Linus Torvalds
2bca25eaeb spi: Updates for v6.1
With the exception of some refactoring to fix long standing issues
 where we weren't handling cache syncs properly for messages which had
 PIO and DMA transfers going to the same page correctly there has been o
 work on the core this time around, and it's also been quite a quiet
 release for the drivers too:
 
  - Fix cache syncs for cases where we have DMA and PIO transfers in the
    same message going to the same page.
  - Update the fsl_spi driver to use transfer_one() rather than a custom
    transfer function.
  - Support for configuring transfer speeds with the AMD SPI controller.
  - Support for a second chip select and 64K erase on Intel SPI.
  - Support for Microchip coreQSPI, Nuvoton NPCM845, NXP i.MX93, and
    Rockchip RK3128 and RK3588.
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Merge tag 'spi-v6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
 "With the exception of some refactoring to fix long standing issues
  where we weren't handling cache syncs properly for messages which had
  PIO and DMA transfers going to the same page correctly there has been
  no work on the core this time around, and it's also been quite a quiet
  release for the drivers too:

   - Fix cache syncs for cases where we have DMA and PIO transfers in
     the same message going to the same page

   - Update the fsl_spi driver to use transfer_one() rather than a
     custom transfer function

   - Support for configuring transfer speeds with the AMD SPI controller

   - Support for a second chip select and 64K erase on Intel SPI

   - Support for Microchip coreQSPI, Nuvoton NPCM845, NXP i.MX93, and
     Rockchip RK3128 and RK3588"

* tag 'spi-v6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (73 commits)
  spi: Ensure that sg_table won't be used after being freed
  spi: spi-gxp: Use devm_platform_ioremap_resource()
  spi: s3c64xx: Fix large transfers with DMA
  spi: Split transfers larger than max size
  spi: Fix cache corruption due to DMA/PIO overlap
  spi: Save current RX and TX DMA devices
  spi: mt65xx: Add dma max segment size declaration
  spi: migrate mt7621 text bindings to YAML
  spi: renesas,sh-msiof: Add r8a779g0 support
  spi: spi-fsl-qspi: Use devm_platform_ioremap_resource_byname()
  spi: spi-fsl-lpspi: Use devm_platform_get_and_ioremap_resource()
  spi: spi-fsl-dspi: Use devm_platform_get_and_ioremap_resource()
  spi/omap100k:Fix PM disable depth imbalance in omap1_spi100k_probe
  spi: dw: Fix PM disable depth imbalance in dw_spi_bt1_probe
  spi: cadence-quadspi: Fix PM disable depth imbalance in cqspi_probe
  spi: s3c24xx: Switch to use devm_spi_alloc_master()
  spi: xilinx: Switch to use devm_spi_alloc_master()
  spi: img-spfi: using pm_runtime_resume_and_get instead of pm_runtime_get_sync
  spi: aspeed: Remove redundant dev_err call
  spi: spi-mpc52xx: switch to using gpiod API
  ...
2022-10-04 19:36:53 -07:00
Zhang Qilong
4d0ef0a1c3
spi: cadence-quadspi: Fix PM disable depth imbalance in cqspi_probe
The pm_runtime_enable will increase power disable depth. Thus
a pairing decrement is needed on the error handling path to
keep it balanced according to context.

Fixes:73d5fe0462702 ("spi: cadence-quadspi: Remove spi_master_put() in probe failure path")

Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
Link: https://lore.kernel.org/r/20220924121310.78331-2-zhangqilong3@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-26 16:10:35 +01:00
Niravkumar L Rabara
9ee5b6d53b
spi: cadence-quadspi: Disable irqs during indirect reads
On architecture where reading the SRAM is slower than the pace at
controller fills it, with interrupt enabled while reading from
SRAM FIFO causes unwanted interrupt storm to CPU.

The inner "bytes to read" loop never exits and waits for the completion
so it is enough to only enable the watermark interrupt when we
are out of bytes to read, which only happens when we start the
transfer (waiting for the FIFO to fill up initially) if the SRAM
is slow.

So only using read watermark interrupt, as the current implementation
doesn't utilize the SRAM full and indirect complete read interrupt.
And disable all the read interrupts while reading from SRAM.

Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Link: https://lore.kernel.org/r/20220813042616.1372110-1-niravkumar.l.rabara@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-22 14:05:21 +01:00
Vaishnav Achath
73d5fe0462
spi: cadence-quadspi: Remove spi_master_put() in probe failure path
Currently the spi_master is allocated by devm_spi_alloc_master()
and devres core manages the deallocation, but in probe failure
path spi_master_put() is being handled manually which causes
"refcount underflow use-after-free" warning when probe failure happens
after allocating spi_master.

Trimmed backtrace during failure:

refcount_t: underflow; use-after-free.
pc : refcount_warn_saturate+0xf4/0x144
Call trace:
refcount_warn_saturate
kobject_put
put_device
devm_spi_release_controller
devres_release_all

This commit makes relevant changes to remove spi_master_put() from probe
failure path.

Fixes: 606e5d4081 ("spi: cadence-quadspi: Handle spi_unregister_master() in remove()")

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20220601071611.11853-1-vaishnav.a@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-14 13:26:35 +01:00
Vaishnav Achath
606e5d4081
spi: cadence-quadspi: Handle spi_unregister_master() in remove()
Currently devres managed removal of the spi_controller happens after
removing the power domain of the host platform_device.While this
does not affect the clean removal of the controller, but affects
graceful removal of the child devices if the child  device removal
requires issuing commands over SPI.

Eg. flash device being soft reset to 1S-1S-1S mode before removal
so that on next probe operations in 1S-1S-1S mode is successful.

Failure is seen when `rmmod spi-cadence-quadspi` is performed:

root@j7-evm:~# rmmod spi_cadence_quadspi
[ 49.230996] cadence-qspi 47050000.spi: QSPI is still busy after 500ms timeout.
[ 49.238209] spi-nor spi1.0: operation failed with -110
[ 49.244457] spi-nor spi1.0: Software reset failed: -110

and on subsequent modprobe the OSPI flash probe fails as it
is in 8D-8D-8D mode since the previous soft reset did not happen.

root@j7-evm:~# modprobe spi_cadence_quadspi
[ 73.253536] spi-nor spi0.0: unrecognized JEDEC id bytes: ff ff ff ff ff ff
[ 73.260476] spi-nor: probe of spi0.0 failed with error -2

This commit adds necessary changes to perform spi_unregister_master()
in the host device remove() so that the child devices are gracefully
removed before the power domain is removed.

changes tested on J721E with mt35xu512aba flash.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20220511115516.14894-1-vaishnav.a@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-12 15:43:03 +01:00
Mark Brown
d5efbfc521
spi: stm32-qspi: flags management fixes
Merge series from patrice.chotard@foss.st.com <patrice.chotard@foss.st.com>
Patrice Chotard <patrice.chotard@foss.st.com>:

From: Patrice Chotard <patrice.chotard@foss.st.com>

This series update flags management in the following cases:
  - In APM mode, don't take care of TCF and TEF flags
  - Always check TCF flag in stm32_qspi_wait_cmd()
  - Don't check BUSY flag when sending new command
2022-05-11 19:48:07 +01:00
Ian Abbott
0d8688298d
spi: cadence-quadspi: remove unnecessary (void *) casts
Remove a couple of unnecessary casts to `(void *)` when initializing the
`.data` members in the device ID table.

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Link: https://lore.kernel.org/r/20220510115141.212779-3-abbotti@mev.co.uk
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-10 14:01:59 +01:00