spi: cadence-quadspi: Disable the SPI before reconfiguring
Observed random DMA timeout failures while doing back to back transfers which involves switching the modes from DMA to NON-DMA. This issue is observed while testing the OSPI+UBIFS file system test case where rootfs is mounted from OSPI UBIFS partition. To avoid this issue, disable the SPI before changing the configuration from external DMA to NON-DMA and vice versa and reenable it after changing the configuration. As per the Cadence Octal SPI design specification, it is recommended to disable the Octal-SPI enable bit before reconfiguring. Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Link: https://lore.kernel.org/r/20230320095931.2651714-3-sai.krishna.potthuri@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -791,6 +791,21 @@ failrd:
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return ret;
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}
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static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
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{
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void __iomem *reg_base = cqspi->iobase;
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unsigned int reg;
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reg = readl(reg_base + CQSPI_REG_CONFIG);
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if (enable)
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reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
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else
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reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
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writel(reg, reg_base + CQSPI_REG_CONFIG);
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}
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static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata,
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u_char *rxbuf, loff_t from_addr,
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size_t n_rx)
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@ -815,10 +830,14 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata,
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if (ret)
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return ret;
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cqspi_controller_enable(cqspi, 0);
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reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
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reg |= CQSPI_REG_CONFIG_DMA_MASK;
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writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
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cqspi_controller_enable(cqspi, 1);
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dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE);
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if (dma_mapping_error(dev, dma_addr)) {
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dev_err(dev, "dma mapping failed\n");
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@ -876,10 +895,14 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata,
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cqspi->iobase + CQSPI_REG_INDIRECTRD);
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dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
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cqspi_controller_enable(cqspi, 0);
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reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
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reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
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writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
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cqspi_controller_enable(cqspi, 1);
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ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
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PM_OSPI_MUX_SEL_LINEAR);
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if (ret)
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@ -1182,21 +1205,6 @@ static void cqspi_readdata_capture(struct cqspi_st *cqspi,
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writel(reg, reg_base + CQSPI_REG_READCAPTURE);
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}
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static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
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{
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void __iomem *reg_base = cqspi->iobase;
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unsigned int reg;
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reg = readl(reg_base + CQSPI_REG_CONFIG);
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if (enable)
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reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
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else
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reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
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writel(reg, reg_base + CQSPI_REG_CONFIG);
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}
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static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
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unsigned long sclk)
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{
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