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PCI: Mask Replay Timer Timeout errors for Genesys GL975x SD host controller

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Due to a hardware defect in GL975x, config accesses when ASPM is enabled
frequently cause Replay Timer Timeouts in the Port leading to the device.

These are Correctable Errors, so the Downstream Port logs it in its AER
Correctable Error Status register and, when the error is not masked, sends
an ERR_COR message upstream.  The message terminates at a Root Port, which
may generate an AER interrupt so the OS can log it.

The Correctable Error logging is an annoyance but not a major issue itself.
But when the AER interrupt happens during suspend, it can prevent the
system from suspending.

015c9cbcf0 ("mmc: sdhci-pci-gli: GL9750: Mask the replay timer timeout of
AER") masked these errors in the GL975x itself.

Mask these errors in the Port leading to GL975x as well.  Note that Replay
Timer Timeouts will still be logged in the AER Correctable Error Status
register, but they will not cause AER interrupts.

Link: https://lore.kernel.org/r/20240327024509.1071189-1-kai.heng.feng@canonical.com
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
[bhelgaas: commit log, update dmesg note]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Victor Shih <victor.shih@genesyslogic.com.tw>
Cc: Ben Chuang <benchuanggli@gmail.com>
This commit is contained in:
Kai-Heng Feng 2024-03-27 10:45:09 +08:00 committed by Bjorn Helgaas
parent 4cece76496
commit eeee3b5e6d
1 changed files with 20 additions and 0 deletions
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20
drivers/pci/quirks.c
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@ -6261,3 +6261,23 @@ static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev)
pdev->d3cold_delay = 1000;
}
DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec);
#ifdef CONFIG_PCIEAER
static void pci_mask_replay_timer_timeout(struct pci_dev *pdev)
{
struct pci_dev *parent = pci_upstream_bridge(pdev);
u32 val;
if (!parent || !parent->aer_cap)
return;
pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect",
pci_name(pdev));
pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val);
val |= PCI_ERR_COR_REP_TIMER;
pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout);
#endif