From eeee3b5e6d0bf331befa57b4dcb079f827bcd829 Mon Sep 17 00:00:00 2001 From: Kai-Heng Feng Date: Wed, 27 Mar 2024 10:45:09 +0800 Subject: [PATCH] PCI: Mask Replay Timer Timeout errors for Genesys GL975x SD host controller Due to a hardware defect in GL975x, config accesses when ASPM is enabled frequently cause Replay Timer Timeouts in the Port leading to the device. These are Correctable Errors, so the Downstream Port logs it in its AER Correctable Error Status register and, when the error is not masked, sends an ERR_COR message upstream. The message terminates at a Root Port, which may generate an AER interrupt so the OS can log it. The Correctable Error logging is an annoyance but not a major issue itself. But when the AER interrupt happens during suspend, it can prevent the system from suspending. 015c9cbcf0ad ("mmc: sdhci-pci-gli: GL9750: Mask the replay timer timeout of AER") masked these errors in the GL975x itself. Mask these errors in the Port leading to GL975x as well. Note that Replay Timer Timeouts will still be logged in the AER Correctable Error Status register, but they will not cause AER interrupts. Link: https://lore.kernel.org/r/20240327024509.1071189-1-kai.heng.feng@canonical.com Signed-off-by: Kai-Heng Feng [bhelgaas: commit log, update dmesg note] Signed-off-by: Bjorn Helgaas Cc: Victor Shih Cc: Ben Chuang --- drivers/pci/quirks.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index bf4833221816..5cb0f7fae3b8 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -6261,3 +6261,23 @@ static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) pdev->d3cold_delay = 1000; } DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); + +#ifdef CONFIG_PCIEAER +static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) +{ + struct pci_dev *parent = pci_upstream_bridge(pdev); + u32 val; + + if (!parent || !parent->aer_cap) + return; + + pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect", + pci_name(pdev)); + + pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val); + val |= PCI_ERR_COR_REP_TIMER; + pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val); +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); +#endif