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i2c-for-6.12-rc1-additional_fixes

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I2C host fixes for v6.12-rc1 (from Andi)
 
 The DesignWare driver now has the correct ENABLE-ABORT sequence,
 ensuring ABORT can always be sent when needed.
 
 In the SynQuacer controller we now check for PCLK as an optional
 clock, allowing ACPI to directly provide the clock rate.
 
 The recent KEBA driver required a dependency fix in Kconfig.
 
 The XIIC driver now has a corrected power suspend sequence.
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Merge tag 'i2c-for-6.12-rc1-additional_fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Pull i2c fixes from Wolfram Sang:

 - fix DesignWare driver ENABLE-ABORT sequence, ensuring ABORT can
   always be sent when needed

 - check for PCLK in the SynQuacer controller as an optional clock,
   allowing ACPI to directly provide the clock rate

 - KEBA driver Kconfig dependency fix

 - fix XIIC driver power suspend sequence

* tag 'i2c-for-6.12-rc1-additional_fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
  i2c: xiic: Fix pm_runtime_set_suspended() with runtime pm enabled
  i2c: keba: I2C_KEBA should depend on KEBA_CP500
  i2c: synquacer: Deal with optional PCLK correctly
  i2c: designware: fix controller is holding SCL low while ENABLE bit is disabled
This commit is contained in:
Linus Torvalds 2024-09-29 09:47:33 -07:00
commit 907537f570
6 changed files with 58 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/i2c/busses/Kconfig
View File

@ -782,6 +782,7 @@ config I2C_JZ4780
config I2C_KEBA
tristate "KEBA I2C controller support"
depends on HAS_IOMEM
depends on KEBA_CP500 || COMPILE_TEST
select AUXILIARY_BUS
help
This driver supports the I2C controller found in KEBA system FPGA

14
drivers/i2c/busses/i2c-designware-common.c
View File

@ -523,6 +523,7 @@ err_release_lock:
void __i2c_dw_disable(struct dw_i2c_dev *dev)
{
struct i2c_timings *t = &dev->timings;
unsigned int raw_intr_stats;
unsigned int enable;
int timeout = 100;
@ -535,6 +536,19 @@ void __i2c_dw_disable(struct dw_i2c_dev *dev)
abort_needed = raw_intr_stats & DW_IC_INTR_MST_ON_HOLD;
if (abort_needed) {
if (!(enable & DW_IC_ENABLE_ENABLE)) {
regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE);
/*
* Wait 10 times the signaling period of the highest I2C
* transfer supported by the driver (for 400KHz this is
* 25us) to ensure the I2C ENABLE bit is already set
* as described in the DesignWare I2C databook.
*/
fsleep(DIV_ROUND_CLOSEST_ULL(10 * MICRO, t->bus_freq_hz));
/* Set ENABLE bit before setting ABORT */
enable |= DW_IC_ENABLE_ENABLE;
}
regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT);
ret = regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable,
!(enable & DW_IC_ENABLE_ABORT), 10,

1
drivers/i2c/busses/i2c-designware-core.h
View File

@ -108,6 +108,7 @@
DW_IC_INTR_RX_UNDER | \
DW_IC_INTR_RD_REQ)
#define DW_IC_ENABLE_ENABLE BIT(0)
#define DW_IC_ENABLE_ABORT BIT(1)
#define DW_IC_STATUS_ACTIVITY BIT(0)

38
drivers/i2c/busses/i2c-designware-master.c
View File

@ -271,6 +271,34 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
__i2c_dw_write_intr_mask(dev, DW_IC_INTR_MASTER_MASK);
}
/*
* This function waits for the controller to be idle before disabling I2C
* When the controller is not in the IDLE state, the MST_ACTIVITY bit
* (IC_STATUS[5]) is set.
*
* Values:
* 0x1 (ACTIVE): Controller not idle
* 0x0 (IDLE): Controller is idle
*
* The function is called after completing the current transfer.
*
* Returns:
* False when the controller is in the IDLE state.
* True when the controller is in the ACTIVE state.
*/
static bool i2c_dw_is_controller_active(struct dw_i2c_dev *dev)
{
u32 status;
regmap_read(dev->map, DW_IC_STATUS, &status);
if (!(status & DW_IC_STATUS_MASTER_ACTIVITY))
return false;
return regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
!(status & DW_IC_STATUS_MASTER_ACTIVITY),
1100, 20000) != 0;
}
static int i2c_dw_check_stopbit(struct dw_i2c_dev *dev)
{
u32 val;
@ -806,6 +834,16 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
goto done;
}
/*
* This happens rarely (~1:500) and is hard to reproduce. Debug trace
* showed that IC_STATUS had value of 0x23 when STOP_DET occurred,
* if disable IC_ENABLE.ENABLE immediately that can result in
* IC_RAW_INTR_STAT.MASTER_ON_HOLD holding SCL low. Check if
* controller is still ACTIVE before disabling I2C.
*/
if (i2c_dw_is_controller_active(dev))
dev_err(dev->dev, "controller active\n");
/*
* We must disable the adapter before returning and signaling the end
* of the current transfer. Otherwise the hardware might continue

5
drivers/i2c/busses/i2c-synquacer.c
View File

@ -550,12 +550,13 @@ static int synquacer_i2c_probe(struct platform_device *pdev)
device_property_read_u32(&pdev->dev, "socionext,pclk-rate",
&i2c->pclkrate);
pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk");
if (IS_ERR(pclk))
return dev_err_probe(&pdev->dev, PTR_ERR(pclk),
"failed to get and enable clock\n");
i2c->pclkrate = clk_get_rate(pclk);
if (pclk)
i2c->pclkrate = clk_get_rate(pclk);
if (i2c->pclkrate < SYNQUACER_I2C_MIN_CLK_RATE ||
i2c->pclkrate > SYNQUACER_I2C_MAX_CLK_RATE)

2
drivers/i2c/busses/i2c-xiic.c
View File

@ -1337,8 +1337,8 @@ static int xiic_i2c_probe(struct platform_device *pdev)
return 0;
err_pm_disable:
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_disable(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
return ret;
}