I2C host fixes for v6.12-rc1
The DesignWare driver now has the correct ENABLE-ABORT sequence, ensuring ABORT can always be sent when needed. In the SynQuacer controller we now check for PCLK as an optional clock, allowing ACPI to directly provide the clock rate. The recent KEBA driver required a dependency fix in Kconfig. The XIIC driver now has a corrected power suspend sequence. -----BEGIN PGP SIGNATURE----- iIwEABYIADQWIQScDfrjQa34uOld1VLaeAVmJtMtbgUCZvbXjhYcYW5kaS5zaHl0 aUBrZXJuZWwub3JnAAoJENp4BWYm0y1uqzIA/i0qw7iDpHOrCBxOP+hitKE+fM4+ 8Mv5KgL2ALpNQlacAQCWGx2ySTt7To6Ni3HBFn8iABaN9qa3NiiHF1WdcGqJAQ== =LhPE -----END PGP SIGNATURE----- Merge tag 'i2c-host-fixes-6.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-current I2C host fixes for v6.12-rc1 The DesignWare driver now has the correct ENABLE-ABORT sequence, ensuring ABORT can always be sent when needed. In the SynQuacer controller we now check for PCLK as an optional clock, allowing ACPI to directly provide the clock rate. The recent KEBA driver required a dependency fix in Kconfig. The XIIC driver now has a corrected power suspend sequence.
This commit is contained in:
Wolfram Sang
commit
26de8614d8
@ -782,6 +782,7 @@ config I2C_JZ4780
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config I2C_KEBA
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tristate "KEBA I2C controller support"
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depends on HAS_IOMEM
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depends on KEBA_CP500 || COMPILE_TEST
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select AUXILIARY_BUS
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help
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This driver supports the I2C controller found in KEBA system FPGA
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@ -523,6 +523,7 @@ err_release_lock:
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void __i2c_dw_disable(struct dw_i2c_dev *dev)
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{
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struct i2c_timings *t = &dev->timings;
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unsigned int raw_intr_stats;
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unsigned int enable;
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int timeout = 100;
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@ -535,6 +536,19 @@ void __i2c_dw_disable(struct dw_i2c_dev *dev)
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abort_needed = raw_intr_stats & DW_IC_INTR_MST_ON_HOLD;
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if (abort_needed) {
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if (!(enable & DW_IC_ENABLE_ENABLE)) {
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regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE);
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/*
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* Wait 10 times the signaling period of the highest I2C
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* transfer supported by the driver (for 400KHz this is
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* 25us) to ensure the I2C ENABLE bit is already set
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* as described in the DesignWare I2C databook.
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*/
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fsleep(DIV_ROUND_CLOSEST_ULL(10 * MICRO, t->bus_freq_hz));
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/* Set ENABLE bit before setting ABORT */
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enable |= DW_IC_ENABLE_ENABLE;
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}
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regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT);
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ret = regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable,
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!(enable & DW_IC_ENABLE_ABORT), 10,
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@ -108,6 +108,7 @@
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DW_IC_INTR_RX_UNDER | \
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DW_IC_INTR_RD_REQ)
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#define DW_IC_ENABLE_ENABLE BIT(0)
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#define DW_IC_ENABLE_ABORT BIT(1)
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#define DW_IC_STATUS_ACTIVITY BIT(0)
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@ -271,6 +271,34 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
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__i2c_dw_write_intr_mask(dev, DW_IC_INTR_MASTER_MASK);
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}
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/*
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* This function waits for the controller to be idle before disabling I2C
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* When the controller is not in the IDLE state, the MST_ACTIVITY bit
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* (IC_STATUS[5]) is set.
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*
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* Values:
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* 0x1 (ACTIVE): Controller not idle
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* 0x0 (IDLE): Controller is idle
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*
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* The function is called after completing the current transfer.
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*
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* Returns:
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* False when the controller is in the IDLE state.
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* True when the controller is in the ACTIVE state.
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*/
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static bool i2c_dw_is_controller_active(struct dw_i2c_dev *dev)
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{
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u32 status;
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regmap_read(dev->map, DW_IC_STATUS, &status);
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if (!(status & DW_IC_STATUS_MASTER_ACTIVITY))
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return false;
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return regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
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!(status & DW_IC_STATUS_MASTER_ACTIVITY),
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1100, 20000) != 0;
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}
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static int i2c_dw_check_stopbit(struct dw_i2c_dev *dev)
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{
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u32 val;
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@ -806,6 +834,16 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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goto done;
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}
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/*
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* This happens rarely (~1:500) and is hard to reproduce. Debug trace
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* showed that IC_STATUS had value of 0x23 when STOP_DET occurred,
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* if disable IC_ENABLE.ENABLE immediately that can result in
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* IC_RAW_INTR_STAT.MASTER_ON_HOLD holding SCL low. Check if
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* controller is still ACTIVE before disabling I2C.
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*/
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if (i2c_dw_is_controller_active(dev))
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dev_err(dev->dev, "controller active\n");
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/*
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* We must disable the adapter before returning and signaling the end
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* of the current transfer. Otherwise the hardware might continue
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@ -550,12 +550,13 @@ static int synquacer_i2c_probe(struct platform_device *pdev)
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device_property_read_u32(&pdev->dev, "socionext,pclk-rate",
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&i2c->pclkrate);
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pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
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pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk");
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if (IS_ERR(pclk))
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return dev_err_probe(&pdev->dev, PTR_ERR(pclk),
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"failed to get and enable clock\n");
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i2c->pclkrate = clk_get_rate(pclk);
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if (pclk)
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i2c->pclkrate = clk_get_rate(pclk);
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if (i2c->pclkrate < SYNQUACER_I2C_MIN_CLK_RATE ||
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i2c->pclkrate > SYNQUACER_I2C_MAX_CLK_RATE)
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@ -1337,8 +1337,8 @@ static int xiic_i2c_probe(struct platform_device *pdev)
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return 0;
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err_pm_disable:
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pm_runtime_set_suspended(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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return ret;
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}
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