License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 07:07:57 -07:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2005-11-19 02:17:32 -07:00
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#ifndef _ASM_POWERPC_PGTABLE_H
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#define _ASM_POWERPC_PGTABLE_H
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2007-06-12 21:52:56 -07:00
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#ifndef __ASSEMBLY__
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2013-11-18 02:28:13 -07:00
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#include <linux/mmdebug.h>
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2014-08-08 16:40:42 -07:00
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#include <linux/mmzone.h>
|
2007-06-12 21:52:56 -07:00
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#include <asm/processor.h> /* For TASK_SIZE */
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#include <asm/mmu.h>
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#include <asm/page.h>
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2018-05-29 07:28:41 -07:00
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#include <asm/tlbflush.h>
|
powerpc/mm: Rework I$/D$ coherency (v3)
This patch reworks the way we do I and D cache coherency on PowerPC.
The "old" way was split in 3 different parts depending on the processor type:
- Hash with per-page exec support (64-bit and >= POWER4 only) does it
at hashing time, by preventing exec on unclean pages and cleaning pages
on exec faults.
- Everything without per-page exec support (32-bit hash, 8xx, and
64-bit < POWER4) does it for all page going to user space in update_mmu_cache().
- Embedded with per-page exec support does it from do_page_fault() on
exec faults, in a way similar to what the hash code does.
That leads to confusion, and bugs. For example, the method using update_mmu_cache()
is racy on SMP where another processor can see the new PTE and hash it in before
we have cleaned the cache, and then blow trying to execute. This is hard to hit but
I think it has bitten us in the past.
Also, it's inefficient for embedded where we always end up having to do at least
one more page fault.
This reworks the whole thing by moving the cache sync into two main call sites,
though we keep different behaviours depending on the HW capability. The call
sites are set_pte_at() which is now made out of line, and ptep_set_access_flags()
which joins the former in pgtable.c
The base idea for Embedded with per-page exec support, is that we now do the
flush at set_pte_at() time when coming from an exec fault, which allows us
to avoid the double fault problem completely (we can even improve the situation
more by implementing TLB preload in update_mmu_cache() but that's for later).
If for some reason we didn't do it there and we try to execute, we'll hit
the page fault, which will do a minor fault, which will hit ptep_set_access_flags()
to do things like update _PAGE_ACCESSED or _PAGE_DIRTY if needed, we just make
this guys also perform the I/D cache sync for exec faults now. This second path
is the catch all for things that weren't cleaned at set_pte_at() time.
For cpus without per-pag exec support, we always do the sync at set_pte_at(),
thus guaranteeing that when the PTE is visible to other processors, the cache
is clean.
For the 64-bit hash with per-page exec support case, we keep the old mechanism
for now. I'll look into changing it later, once I've reworked a bit how we
use _PAGE_EXEC.
This is also a first step for adding _PAGE_EXEC support for embedded platforms
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-10 09:02:37 -07:00
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|
|
|
2007-06-12 21:52:56 -07:00
|
|
|
struct mm_struct;
|
powerpc/mm: Rework I$/D$ coherency (v3)
This patch reworks the way we do I and D cache coherency on PowerPC.
The "old" way was split in 3 different parts depending on the processor type:
- Hash with per-page exec support (64-bit and >= POWER4 only) does it
at hashing time, by preventing exec on unclean pages and cleaning pages
on exec faults.
- Everything without per-page exec support (32-bit hash, 8xx, and
64-bit < POWER4) does it for all page going to user space in update_mmu_cache().
- Embedded with per-page exec support does it from do_page_fault() on
exec faults, in a way similar to what the hash code does.
That leads to confusion, and bugs. For example, the method using update_mmu_cache()
is racy on SMP where another processor can see the new PTE and hash it in before
we have cleaned the cache, and then blow trying to execute. This is hard to hit but
I think it has bitten us in the past.
Also, it's inefficient for embedded where we always end up having to do at least
one more page fault.
This reworks the whole thing by moving the cache sync into two main call sites,
though we keep different behaviours depending on the HW capability. The call
sites are set_pte_at() which is now made out of line, and ptep_set_access_flags()
which joins the former in pgtable.c
The base idea for Embedded with per-page exec support, is that we now do the
flush at set_pte_at() time when coming from an exec fault, which allows us
to avoid the double fault problem completely (we can even improve the situation
more by implementing TLB preload in update_mmu_cache() but that's for later).
If for some reason we didn't do it there and we try to execute, we'll hit
the page fault, which will do a minor fault, which will hit ptep_set_access_flags()
to do things like update _PAGE_ACCESSED or _PAGE_DIRTY if needed, we just make
this guys also perform the I/D cache sync for exec faults now. This second path
is the catch all for things that weren't cleaned at set_pte_at() time.
For cpus without per-pag exec support, we always do the sync at set_pte_at(),
thus guaranteeing that when the PTE is visible to other processors, the cache
is clean.
For the 64-bit hash with per-page exec support case, we keep the old mechanism
for now. I'll look into changing it later, once I've reworked a bit how we
use _PAGE_EXEC.
This is also a first step for adding _PAGE_EXEC support for embedded platforms
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-10 09:02:37 -07:00
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|
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|
2007-06-12 21:52:56 -07:00
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#endif /* !__ASSEMBLY__ */
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|
2015-11-30 20:36:28 -07:00
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#ifdef CONFIG_PPC_BOOK3S
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#include <asm/book3s/pgtable.h>
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#else
|
2015-11-30 20:36:38 -07:00
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#include <asm/nohash/pgtable.h>
|
2015-11-30 20:36:28 -07:00
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#endif /* !CONFIG_PPC_BOOK3S */
|
2005-04-16 15:20:36 -07:00
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2022-09-07 03:05:01 -07:00
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/*
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* Protection used for kernel text. We want the debuggers to be able to
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* set breakpoints anywhere, so don't write protect the kernel text
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* on platforms where such control is possible.
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*/
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|
#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
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defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
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#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
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#else
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#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
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#endif
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/* Make modules code happy. We don't set RO yet */
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#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
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/* Advertise special mapping type for AGP */
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#define PAGE_AGP (PAGE_KERNEL_NC)
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#define HAVE_PAGE_AGP
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2005-04-16 15:20:36 -07:00
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#ifndef __ASSEMBLY__
|
2008-12-18 12:13:51 -07:00
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2024-01-29 05:46:38 -07:00
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#define PFN_PTE_SHIFT PTE_RPN_SHIFT
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2023-08-02 08:13:49 -07:00
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void set_ptes(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
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pte_t pte, unsigned int nr);
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#define set_ptes set_ptes
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#define update_mmu_cache(vma, addr, ptep) \
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update_mmu_cache_range(NULL, vma, addr, ptep, 1)
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|
2021-06-07 03:56:05 -07:00
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#ifndef MAX_PTRS_PER_PGD
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#define MAX_PTRS_PER_PGD PTRS_PER_PGD
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#endif
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|
2009-03-19 12:34:09 -07:00
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/* Keep these as a macros to avoid include dependency mess */
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
|
2023-08-02 08:13:49 -07:00
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static inline unsigned long pte_pfn(pte_t pte)
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{
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|
return (pte_val(pte) & PTE_RPN_MASK) >> PTE_RPN_SHIFT;
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}
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|
2018-10-17 02:39:21 -07:00
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|
/*
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|
* Select all bits except the pfn
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*/
|
2024-08-26 13:43:42 -07:00
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#define pte_pgprot pte_pgprot
|
2018-10-17 02:39:21 -07:00
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static inline pgprot_t pte_pgprot(pte_t pte)
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|
{
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unsigned long pte_flags;
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pte_flags = pte_val(pte) & ~PTE_RPN_MASK;
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return __pgprot(pte_flags);
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}
|
2009-03-19 12:34:09 -07:00
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2023-09-25 11:31:35 -07:00
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static inline pgprot_t pgprot_nx(pgprot_t prot)
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{
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return pte_pgprot(pte_exprotect(__pte(pgprot_val(prot))));
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}
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#define pgprot_nx pgprot_nx
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2020-06-08 21:33:10 -07:00
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#ifndef pmd_page_vaddr
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2023-08-09 01:07:13 -07:00
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static inline const void *pmd_page_vaddr(pmd_t pmd)
|
2020-06-08 21:33:10 -07:00
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{
|
2023-08-09 01:07:13 -07:00
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return __va(pmd_val(pmd) & ~PMD_MASKED_BITS);
|
2020-06-08 21:33:10 -07:00
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}
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#define pmd_page_vaddr pmd_page_vaddr
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#endif
|
2007-06-12 21:52:56 -07:00
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern unsigned long empty_zero_page[];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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extern pgd_t swapper_pg_dir[];
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extern void paging_init(void);
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2021-06-08 18:34:24 -07:00
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void poking_init(void);
|
2007-06-12 21:52:56 -07:00
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2019-08-20 07:07:16 -07:00
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extern unsigned long ioremap_bot;
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2022-07-11 00:05:37 -07:00
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extern const pgprot_t protection_map[16];
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2019-08-20 07:07:16 -07:00
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2017-07-26 23:24:53 -07:00
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/* can we use this in kvm */
|
2016-02-14 18:55:03 -07:00
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unsigned long vmalloc_to_phys(void *vmalloc_addr);
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2018-11-29 07:07:07 -07:00
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void pgtable_cache_add(unsigned int shift);
|
2017-07-13 23:51:23 -07:00
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2024-07-02 06:51:25 -07:00
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#ifdef CONFIG_PPC32
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void __init *early_alloc_pgtable(unsigned long size);
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#endif
|
2020-05-18 22:49:22 -07:00
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pte_t *early_pte_alloc_kernel(pmd_t *pmdp, unsigned long va);
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2017-08-02 06:51:03 -07:00
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#if defined(CONFIG_STRICT_KERNEL_RWX) || defined(CONFIG_PPC32)
|
2017-07-13 23:51:23 -07:00
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void mark_initmem_nx(void);
|
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#else
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static inline void mark_initmem_nx(void) { }
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#endif
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2023-09-25 11:31:19 -07:00
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
|
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int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
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pte_t *ptep, pte_t entry, int dirty);
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2023-09-22 01:04:58 -07:00
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pgprot_t __phys_mem_access_prot(unsigned long pfn, unsigned long size,
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pgprot_t vma_prot);
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2023-09-25 11:31:19 -07:00
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struct file;
|
2023-09-22 01:04:58 -07:00
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static inline pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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unsigned long size, pgprot_t vma_prot)
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|
{
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|
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|
return __phys_mem_access_prot(pfn, size, vma_prot);
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}
|
2023-09-25 11:31:19 -07:00
|
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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2023-09-25 11:31:20 -07:00
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void __update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep);
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/*
|
|
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|
* This gets called at the end of handling a page fault, when
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* the kernel has put a new PTE into the page table for the process.
|
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* We use it to ensure coherency between the i-cache and d-cache
|
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* for the page which has just been mapped in.
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* On machines which use an MMU hash table, we use this to put a
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* corresponding HPTE into the hash table ahead of time, instead of
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* waiting for the inevitable extra hash-table miss exception.
|
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*/
|
|
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static inline void update_mmu_cache_range(struct vm_fault *vmf,
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struct vm_area_struct *vma, unsigned long address,
|
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pte_t *ptep, unsigned int nr)
|
|
|
|
|
{
|
|
|
|
|
if ((mmu_has_feature(MMU_FTR_HPTE_TABLE) && !radix_enabled()) ||
|
|
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|
|
(IS_ENABLED(CONFIG_PPC_E500) && IS_ENABLED(CONFIG_HUGETLB_PAGE)))
|
|
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|
|
__update_mmu_cache(vma, address, ptep);
|
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|
}
|
2023-09-25 11:31:19 -07:00
|
|
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|
2018-11-29 07:06:59 -07:00
|
|
|
/*
|
|
|
|
|
* When used, PTE_FRAG_NR is defined in subarch pgtable.h
|
|
|
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|
* so we are sure it is included when arriving here.
|
|
|
|
|
*/
|
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|
#ifdef PTE_FRAG_NR
|
|
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|
static inline void *pte_frag_get(mm_context_t *ctx)
|
|
|
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|
{
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return ctx->pte_frag;
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|
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}
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static inline void pte_frag_set(mm_context_t *ctx, void *p)
|
|
|
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|
{
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|
|
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|
ctx->pte_frag = p;
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|
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}
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|
|
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|
#else
|
2018-11-29 07:07:01 -07:00
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|
#define PTE_FRAG_NR 1
|
|
|
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|
#define PTE_FRAG_SIZE_SHIFT PAGE_SHIFT
|
|
|
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|
#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
|
|
|
|
|
|
2018-11-29 07:06:59 -07:00
|
|
|
static inline void *pte_frag_get(mm_context_t *ctx)
|
|
|
|
|
{
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void pte_frag_set(mm_context_t *ctx, void *p)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2021-06-30 18:53:59 -07:00
|
|
|
#define pmd_pgtable pmd_pgtable
|
|
|
|
|
static inline pgtable_t pmd_pgtable(pmd_t pmd)
|
|
|
|
|
{
|
|
|
|
|
return (pgtable_t)pmd_page_vaddr(pmd);
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-24 12:07:56 -07:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
int __meminit vmemmap_populated(unsigned long vmemmap_addr, int vmemmap_map_size);
|
|
|
|
|
bool altmap_cross_boundary(struct vmem_altmap *altmap, unsigned long start,
|
|
|
|
|
unsigned long page_size);
|
2023-08-08 02:15:00 -07:00
|
|
|
/*
|
|
|
|
|
* mm/memory_hotplug.c:mhp_supports_memmap_on_memory goes into details
|
|
|
|
|
* some of the restrictions. We don't check for PMD_SIZE because our
|
|
|
|
|
* vmemmap allocation code can fallback correctly. The pageblock
|
|
|
|
|
* alignment requirement is met using altmap->reserve blocks.
|
|
|
|
|
*/
|
|
|
|
|
#define arch_supports_memmap_on_memory arch_supports_memmap_on_memory
|
|
|
|
|
static inline bool arch_supports_memmap_on_memory(unsigned long vmemmap_size)
|
|
|
|
|
{
|
|
|
|
|
if (!radix_enabled())
|
|
|
|
|
return false;
|
|
|
|
|
/*
|
|
|
|
|
* With 4K page size and 2M PMD_SIZE, we can align
|
|
|
|
|
* things better with memory block size value
|
|
|
|
|
* starting from 128MB. Hence align things with PMD_SIZE.
|
|
|
|
|
*/
|
|
|
|
|
if (IS_ENABLED(CONFIG_PPC_4K_PAGES))
|
|
|
|
|
return IS_ALIGNED(vmemmap_size, PMD_SIZE);
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-24 12:07:56 -07:00
|
|
|
#endif /* CONFIG_PPC64 */
|
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
|
2005-11-19 02:17:32 -07:00
|
|
|
#endif /* _ASM_POWERPC_PGTABLE_H */
|