2021-12-09 13:47:24 -07:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2014-10-20 21:28:05 -07:00
|
|
|
|
|
|
|
#include <linux/types.h>
|
2022-05-23 05:16:39 -07:00
|
|
|
#include <linux/dma-map-ops.h>
|
2018-06-15 04:08:52 -07:00
|
|
|
#include <asm/bmips.h>
|
2021-12-09 13:47:24 -07:00
|
|
|
#include <asm/io.h>
|
2014-10-20 21:28:05 -07:00
|
|
|
|
2023-03-17 03:20:04 -07:00
|
|
|
bool bmips_rac_flush_disable;
|
|
|
|
|
2019-11-07 10:03:11 -07:00
|
|
|
void arch_sync_dma_for_cpu_all(void)
|
2018-06-15 04:08:52 -07:00
|
|
|
{
|
2024-06-20 08:26:42 -07:00
|
|
|
void __iomem *cbr = bmips_cbr_addr;
|
2018-06-15 04:08:52 -07:00
|
|
|
u32 cfg;
|
|
|
|
|
|
|
|
if (boot_cpu_type() != CPU_BMIPS3300 &&
|
|
|
|
boot_cpu_type() != CPU_BMIPS4350 &&
|
|
|
|
boot_cpu_type() != CPU_BMIPS4380)
|
|
|
|
return;
|
|
|
|
|
2023-03-17 03:20:04 -07:00
|
|
|
if (unlikely(bmips_rac_flush_disable))
|
|
|
|
return;
|
|
|
|
|
2018-06-15 04:08:52 -07:00
|
|
|
/* Flush stale data out of the readahead cache */
|
|
|
|
cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
|
|
|
|
__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
|
|
|
|
__raw_readl(cbr + BMIPS_RAC_CONFIG);
|
|
|
|
}
|