a5c05453a1
Rework the handling of the CBR address and cache it. This address doesn't change and can be cached instead of reading the register every time. This is in preparation of permitting to tweak the CBR address in DT with broken SoC or bootloader. bmips_cbr_addr is defined in setup.c for each arch to keep compatibility with legacy brcm47xx/brcm63xx and generic BMIPS target. Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
28 lines
626 B
C
28 lines
626 B
C
// SPDX-License-Identifier: GPL-2.0+
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#include <linux/types.h>
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#include <linux/dma-map-ops.h>
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#include <asm/bmips.h>
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#include <asm/io.h>
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bool bmips_rac_flush_disable;
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void arch_sync_dma_for_cpu_all(void)
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{
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void __iomem *cbr = bmips_cbr_addr;
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u32 cfg;
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if (boot_cpu_type() != CPU_BMIPS3300 &&
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boot_cpu_type() != CPU_BMIPS4350 &&
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boot_cpu_type() != CPU_BMIPS4380)
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return;
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if (unlikely(bmips_rac_flush_disable))
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return;
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/* Flush stale data out of the readahead cache */
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cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
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__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
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__raw_readl(cbr + BMIPS_RAC_CONFIG);
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}
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