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86 lines
3.5 KiB
VimL
86 lines
3.5 KiB
VimL
" Vim syntax file
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" Language: SystemVerilog
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" Maintainer: kocha <kocha.lsifrontend@gmail.com>
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" Last Change: 12-Aug-2013.
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" quit when a syntax file was already loaded
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if exists("b:current_syntax")
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finish
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endif
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" Read in Verilog syntax files
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runtime! syntax/verilog.vim
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unlet b:current_syntax
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" IEEE1800-2005
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syn keyword systemverilogStatement always_comb always_ff always_latch
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syn keyword systemverilogStatement class endclass new
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syn keyword systemverilogStatement virtual local const protected
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syn keyword systemverilogStatement package endpackage
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syn keyword systemverilogStatement rand randc constraint randomize
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syn keyword systemverilogStatement with inside dist
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syn keyword systemverilogStatement sequence endsequence randsequence
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syn keyword systemverilogStatement srandom
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syn keyword systemverilogStatement logic bit byte
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syn keyword systemverilogStatement int longint shortint
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syn keyword systemverilogStatement struct packed
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syn keyword systemverilogStatement final
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syn keyword systemverilogStatement import export
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syn keyword systemverilogStatement context pure
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syn keyword systemverilogStatement void shortreal chandle string
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syn keyword systemverilogStatement clocking endclocking iff
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syn keyword systemverilogStatement interface endinterface modport
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syn keyword systemverilogStatement cover covergroup coverpoint endgroup
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syn keyword systemverilogStatement property endproperty
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syn keyword systemverilogStatement program endprogram
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syn keyword systemverilogStatement bins binsof illegal_bins ignore_bins
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syn keyword systemverilogStatement alias matches solve static assert
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syn keyword systemverilogStatement assume super before expect bind
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syn keyword systemverilogStatement extends null tagged extern this
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syn keyword systemverilogStatement first_match throughout timeprecision
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syn keyword systemverilogStatement timeunit type union
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syn keyword systemverilogStatement uwire var cross ref wait_order intersect
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syn keyword systemverilogStatement wildcard within
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syn keyword systemverilogTypeDef typedef enum
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syn keyword systemverilogConditional randcase
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syn keyword systemverilogConditional unique priority
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syn keyword systemverilogRepeat return break continue
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syn keyword systemverilogRepeat do foreach
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syn keyword systemverilogLabel join_any join_none forkjoin
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" IEEE1800-2009 add
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syn keyword systemverilogStatement checker endchecker
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syn keyword systemverilogStatement accept_on reject_on
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syn keyword systemverilogStatement sync_accept_on sync_reject_on
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syn keyword systemverilogStatement eventually nexttime until until_with
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syn keyword systemverilogStatement s_always s_eventually s_nexttime s_until s_until_with
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syn keyword systemverilogStatement let untyped
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syn keyword systemverilogStatement strong weak
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syn keyword systemverilogStatement restrict global implies
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syn keyword systemverilogConditional unique0
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" IEEE1800-2012 add
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syn keyword systemverilogStatement implements
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syn keyword systemverilogStatement interconnect soft nettype
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" Define the default highlighting.
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" The default highlighting.
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hi def link systemverilogStatement Statement
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hi def link systemverilogTypeDef TypeDef
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hi def link systemverilogConditional Conditional
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hi def link systemverilogRepeat Repeat
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hi def link systemverilogLabel Label
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hi def link systemverilogGlobal Define
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hi def link systemverilogNumber Number
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let b:current_syntax = "systemverilog"
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" vim: ts=8
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