b094516f95
Those tuners are currently used only under media/dvb. However, they can support also analog TV. Better to move them to the same place as the other hybrid tuners. This would make easier to use those tuners also by analog drivers. Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
106 lines
4.2 KiB
C
106 lines
4.2 KiB
C
/*
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* Driver for Microtune MT2060 "Single chip dual conversion broadband tuner"
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*
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* Copyright (c) 2006 Olivier DANET <odanet@caramail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
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*/
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#ifndef MT2060_PRIV_H
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#define MT2060_PRIV_H
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// Uncomment the #define below to enable spurs checking. The results where quite unconvincing.
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// #define MT2060_SPURCHECK
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/* This driver is based on the information available in the datasheet of the
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"Comtech SDVBT-3K6M" tuner ( K1000737843.pdf ) which features the MT2060 register map :
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I2C Address : 0x60
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Reg.No | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | ( defaults )
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--------------------------------------------------------------------------------
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00 | [ PART ] | [ REV ] | R = 0x63
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01 | [ LNABAND ] | [ NUM1(5:2) ] | RW = 0x3F
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02 | [ DIV1 ] | RW = 0x74
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03 | FM1CA | FM1SS | [ NUM1(1:0) ] | [ NUM2(3:0) ] | RW = 0x00
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04 | NUM2(11:4) ] | RW = 0x08
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05 | [ DIV2 ] |NUM2(12)| RW = 0x93
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06 | L1LK | [ TAD1 ] | L2LK | [ TAD2 ] | R
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07 | [ FMF ] | R
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08 | ? | FMCAL | ? | ? | ? | ? | ? | TEMP | R
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09 | 0 | 0 | [ FMGC ] | 0 | GP02 | GP01 | 0 | RW = 0x20
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0A | ??
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0B | 0 | 0 | 1 | 1 | 0 | 0 | [ VGAG ] | RW = 0x30
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0C | V1CSE | 1 | 1 | 1 | 1 | 1 | 1 | 1 | RW = 0xFF
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0D | 1 | 0 | [ V1CS ] | RW = 0xB0
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0E | ??
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0F | ??
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10 | ??
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11 | [ LOTO ] | 0 | 0 | 1 | 0 | RW = 0x42
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PART : Part code : 6 for MT2060
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REV : Revision code : 3 for current revision
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LNABAND : Input frequency range : ( See code for details )
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NUM1 / DIV1 / NUM2 / DIV2 : Frequencies programming ( See code for details )
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FM1CA : Calibration Start Bit
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FM1SS : Calibration Single Step bit
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L1LK : LO1 Lock Detect
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TAD1 : Tune Line ADC ( ? )
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L2LK : LO2 Lock Detect
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TAD2 : Tune Line ADC ( ? )
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FMF : Estimated first IF Center frequency Offset ( ? )
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FM1CAL : Calibration done bit
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TEMP : On chip temperature sensor
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FMCG : Mixer 1 Cap Gain ( ? )
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GP01 / GP02 : Programmable digital outputs. Unconnected pins ?
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V1CSE : LO1 VCO Automatic Capacitor Select Enable ( ? )
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V1CS : LO1 Capacitor Selection Value ( ? )
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LOTO : LO Timeout ( ? )
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VGAG : Tuner Output gain
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*/
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#define I2C_ADDRESS 0x60
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#define REG_PART_REV 0
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#define REG_LO1C1 1
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#define REG_LO1C2 2
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#define REG_LO2C1 3
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#define REG_LO2C2 4
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#define REG_LO2C3 5
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#define REG_LO_STATUS 6
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#define REG_FM_FREQ 7
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#define REG_MISC_STAT 8
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#define REG_MISC_CTRL 9
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#define REG_RESERVED_A 0x0A
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#define REG_VGAG 0x0B
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#define REG_LO1B1 0x0C
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#define REG_LO1B2 0x0D
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#define REG_LOTO 0x11
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#define PART_REV 0x63 // The current driver works only with PART=6 and REV=3 chips
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struct mt2060_priv {
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struct mt2060_config *cfg;
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struct i2c_adapter *i2c;
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u32 frequency;
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u32 bandwidth;
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u16 if1_freq;
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u8 fmfreq;
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};
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#endif
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