9a8fd55899
The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
117 lines
3.3 KiB
C
117 lines
3.3 KiB
C
/*
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* linux/include/asm-xtensa/pgalloc.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Copyright (C) 2001-2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_PGALLOC_H
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#define _XTENSA_PGALLOC_H
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#ifdef __KERNEL__
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#include <linux/config.h>
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#include <linux/threads.h>
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#include <linux/highmem.h>
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#include <asm/processor.h>
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#include <asm/cacheflush.h>
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/* Cache aliasing:
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*
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* If the cache size for one way is greater than the page size, we have to
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* deal with cache aliasing. The cache index is wider than the page size:
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*
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* |cache |
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* |pgnum |page| virtual address
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* |xxxxxX|zzzz|
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* | | |
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* \ / | |
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* trans.| |
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* / \ | |
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* |yyyyyY|zzzz| physical address
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*
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* When the page number is translated to the physical page address, the lowest
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* bit(s) (X) that are also part of the cache index are also translated (Y).
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* If this translation changes this bit (X), the cache index is also afected,
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* thus resulting in a different cache line than before.
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* The kernel does not provide a mechanism to ensure that the page color
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* (represented by this bit) remains the same when allocated or when pages
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* are remapped. When user pages are mapped into kernel space, the color of
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* the page might also change.
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*
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* We use the address space VMALLOC_END ... VMALLOC_END + DCACHE_WAY_SIZE * 2
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* to temporarily map a patch so we can match the color.
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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# define PAGE_COLOR_MASK (PAGE_MASK & (DCACHE_WAY_SIZE-1))
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# define PAGE_COLOR(a) \
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(((unsigned long)(a)&PAGE_COLOR_MASK) >> PAGE_SHIFT)
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# define PAGE_COLOR_EQ(a,b) \
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((((unsigned long)(a) ^ (unsigned long)(b)) & PAGE_COLOR_MASK) == 0)
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# define PAGE_COLOR_MAP0(v) \
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(VMALLOC_END + ((unsigned long)(v) & PAGE_COLOR_MASK))
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# define PAGE_COLOR_MAP1(v) \
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(VMALLOC_END + ((unsigned long)(v) & PAGE_COLOR_MASK) + DCACHE_WAY_SIZE)
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#endif
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/*
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* Allocating and freeing a pmd is trivial: the 1-entry pmd is
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* inside the pgd, so has no extra memory associated with it.
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*/
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#define pgd_free(pgd) free_page((unsigned long)(pgd))
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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static inline void
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pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *pte)
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{
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pmd_val(*(pmdp)) = (unsigned long)(pte);
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__asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp));
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}
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static inline void
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pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *page)
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{
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pmd_val(*(pmdp)) = (unsigned long)page_to_virt(page);
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__asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp));
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}
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#else
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# define pmd_populate_kernel(mm, pmdp, pte) \
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(pmd_val(*(pmdp)) = (unsigned long)(pte))
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# define pmd_populate(mm, pmdp, page) \
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(pmd_val(*(pmdp)) = (unsigned long)page_to_virt(page))
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#endif
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static inline pgd_t*
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pgd_alloc(struct mm_struct *mm)
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{
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pgd_t *pgd;
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pgd = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, PGD_ORDER);
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if (likely(pgd != NULL))
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__flush_dcache_page((unsigned long)pgd);
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return pgd;
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}
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extern pte_t* pte_alloc_one_kernel(struct mm_struct* mm, unsigned long addr);
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extern struct page* pte_alloc_one(struct mm_struct* mm, unsigned long addr);
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#define pte_free_kernel(pte) free_page((unsigned long)pte)
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#define pte_free(pte) __free_page(pte)
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_PGALLOC_H */
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