6a01f23033
[Mike Frysinger <vapier.adi@gmail.com>:
- handle bf531/bf532/bf534/bf536 variants in ipipe.h
- cleanup IPIPE logic for bfin_set_irq_handler()
- cleanup ipipe asm code a bit and add missing ENDPROC()
- simplify IPIPE code in trap_c
- unify some of the IPIPE code and fix style
- simplify DO_IRQ_L1 handling with ipipe code
- revert IRQ_SW_INT# addition from ipipe merge
- remove duplicate get_{c,s}clk() prototypes
]
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
95 lines
3.9 KiB
C
95 lines
3.9 KiB
C
/*
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* File: arch/blackfin/mach-bf538/ints-priority.c
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* Based on: arch/blackfin/mach-bf533/ints-priority.c
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* Author: Michael Hennerich
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*
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* Created:
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* Description: Set up the interrupt priorities
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*
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* Modified:
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* Copyright 2008 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <asm/blackfin.h>
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void __init program_IAR(void)
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{
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/* Program the IAR0 Register with the configured priority */
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bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
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((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
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((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
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((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
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((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
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((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) |
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((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
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((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
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bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
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((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
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((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
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((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
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((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
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((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
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((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
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((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
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bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
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((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
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((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
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((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
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((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
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((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) |
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((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) |
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((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
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bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
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((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) |
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((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) |
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((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
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((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) |
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((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
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((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS));
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bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) |
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((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
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((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
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((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
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((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
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((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
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bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
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((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
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((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
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((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) |
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((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) |
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((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
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((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
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((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
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bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
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((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) |
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((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS));
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SSYNC();
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}
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