141 lines
3.6 KiB
C
141 lines
3.6 KiB
C
/* pbm.h: UltraSparc PCI controller software state.
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*
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* Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
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*/
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#ifndef __SPARC64_PBM_H
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#define __SPARC64_PBM_H
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/spinlock.h>
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#include <linux/msi.h>
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#include <asm/io.h>
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#include <asm/page.h>
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#include <asm/oplib.h>
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#include <asm/prom.h>
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#include <asm/of_device.h>
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#include <asm/iommu.h>
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/* The abstraction used here is that there are PCI controllers,
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* each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
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* underneath. Each PCI bus module uses an IOMMU (shared by both
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* PBMs of a controller, or per-PBM), and if a streaming buffer
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* is present, each PCI bus module has it's own. (ie. the IOMMU
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* might be shared between PBMs, the STC is never shared)
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* Furthermore, each PCI bus module controls it's own autonomous
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* PCI bus.
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*/
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extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
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#define PCI_STC_FLUSHFLAG_INIT(STC) \
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(*((STC)->strbuf_flushflag) = 0UL)
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#define PCI_STC_FLUSHFLAG_SET(STC) \
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(*((STC)->strbuf_flushflag) != 0UL)
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struct pci_controller_info;
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struct pci_pbm_info {
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struct pci_pbm_info *next;
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/* PCI controller we sit under. */
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struct pci_controller_info *parent;
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/* Physical address base of controller registers. */
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unsigned long controller_regs;
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/* Physical address base of PBM registers. */
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unsigned long pbm_regs;
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/* Physical address of DMA sync register, if any. */
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unsigned long sync_reg;
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/* Opaque 32-bit system bus Port ID. */
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u32 portid;
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/* Opaque 32-bit handle used for hypervisor calls. */
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u32 devhandle;
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/* Chipset version information. */
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int chip_type;
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#define PBM_CHIP_TYPE_SABRE 1
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#define PBM_CHIP_TYPE_PSYCHO 2
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#define PBM_CHIP_TYPE_SCHIZO 3
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#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
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#define PBM_CHIP_TYPE_TOMATILLO 5
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int chip_version;
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int chip_revision;
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/* Name used for top-level resources. */
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char *name;
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/* OBP specific information. */
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struct device_node *prom_node;
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u64 ino_bitmap;
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/* PBM I/O and Memory space resources. */
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struct resource io_space;
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struct resource mem_space;
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/* Base of PCI Config space, can be per-PBM or shared. */
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unsigned long config_space;
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/* State of 66MHz capabilities on this PBM. */
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int is_66mhz_capable;
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int all_devs_66mhz;
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#ifdef CONFIG_PCI_MSI
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/* MSI info. */
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u32 msiq_num;
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u32 msiq_ent_count;
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u32 msiq_first;
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u32 msiq_first_devino;
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u32 msi_num;
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u32 msi_first;
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u32 msi_data_mask;
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u32 msix_data_width;
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u64 msi32_start;
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u64 msi64_start;
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u32 msi32_len;
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u32 msi64_len;
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void *msi_queues;
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unsigned long *msi_bitmap;
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#endif /* !(CONFIG_PCI_MSI) */
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/* This PBM's streaming buffer. */
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struct strbuf stc;
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/* IOMMU state, potentially shared by both PBM segments. */
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struct iommu *iommu;
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/* Now things for the actual PCI bus probes. */
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unsigned int pci_first_busno;
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unsigned int pci_last_busno;
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struct pci_bus *pci_bus;
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void (*scan_bus)(struct pci_pbm_info *);
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struct pci_ops *pci_ops;
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};
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struct pci_controller_info {
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/* Each controller gets a unique index, used mostly for
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* error logging purposes.
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*/
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int index;
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/* The PCI bus modules controlled by us. */
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struct pci_pbm_info pbm_A;
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struct pci_pbm_info pbm_B;
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/* Operations which are controller specific. */
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#ifdef CONFIG_PCI_MSI
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int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
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struct msi_desc *entry);
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void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
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#endif
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};
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#endif /* !(__SPARC64_PBM_H) */
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