ed36959621
Add support for the VIA IDE controller that exists on the MPC8555 CDS system. Updated the config for the system to enable support by default. Signed-off-by: Scott Hall <shall@mvista.com> Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
84 lines
2.4 KiB
C
84 lines
2.4 KiB
C
/*
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* arch/ppc/platforms/85xx/mpc85xx_cds_common.h
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*
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* MPC85xx CDS board definitions
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*
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* Maintainer: Kumar Gala <kumar.gala@freescale.com>
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*
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* Copyright 2004 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __MACH_MPC85XX_CDS_H__
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#define __MACH_MPC85XX_CDS_H__
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#include <linux/config.h>
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#include <linux/serial.h>
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#include <asm/ppcboot.h>
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#include <linux/initrd.h>
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#include <syslib/ppc85xx_setup.h>
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#define BOARD_CCSRBAR ((uint)0xe0000000)
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#define CCSRBAR_SIZE ((uint)1024*1024)
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/* CADMUS info */
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#define CADMUS_BASE (0xf8004000)
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#define CADMUS_SIZE (256)
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#define CM_VER (0)
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#define CM_CSR (1)
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#define CM_RST (2)
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/* CDS NVRAM/RTC */
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#define CDS_RTC_ADDR (0xf8000000)
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#define CDS_RTC_SIZE (8 * 1024)
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/* PCI config */
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#define PCI1_CFG_ADDR_OFFSET (0x8000)
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#define PCI1_CFG_DATA_OFFSET (0x8004)
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#define PCI2_CFG_ADDR_OFFSET (0x9000)
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#define PCI2_CFG_DATA_OFFSET (0x9004)
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/* PCI interrupt controller */
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#define PIRQ0A MPC85xx_IRQ_EXT0
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#define PIRQ0B MPC85xx_IRQ_EXT1
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#define PIRQ0C MPC85xx_IRQ_EXT2
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#define PIRQ0D MPC85xx_IRQ_EXT3
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#define PIRQ1A MPC85xx_IRQ_EXT11
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/* PCI 1 memory map */
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#define MPC85XX_PCI1_LOWER_IO 0x00000000
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#define MPC85XX_PCI1_UPPER_IO 0x00ffffff
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#define MPC85XX_PCI1_LOWER_MEM 0x80000000
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#define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
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#define MPC85XX_PCI1_IO_BASE 0xe2000000
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#define MPC85XX_PCI1_MEM_OFFSET 0x00000000
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#define MPC85XX_PCI1_IO_SIZE 0x01000000
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/* PCI 2 memory map */
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/* Note: the standard PPC fixups will cause IO space to get bumped by
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* hose->io_base_virt - isa_io_base => MPC85XX_PCI1_IO_SIZE */
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#define MPC85XX_PCI2_LOWER_IO 0x00000000
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#define MPC85XX_PCI2_UPPER_IO 0x00ffffff
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#define MPC85XX_PCI2_LOWER_MEM 0xa0000000
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#define MPC85XX_PCI2_UPPER_MEM 0xbfffffff
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#define MPC85XX_PCI2_IO_BASE 0xe3000000
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#define MPC85XX_PCI2_MEM_OFFSET 0x00000000
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#define MPC85XX_PCI2_IO_SIZE 0x01000000
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#define NR_8259_INTS 16
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#define CPM_IRQ_OFFSET NR_8259_INTS
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#endif /* __MACH_MPC85XX_CDS_H__ */
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