1fa9be72b5
For systems where the core cycles are not a usable tick source (like SMP or cycles gets updated), enable gptimer0 as an alternative. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
368 lines
8.6 KiB
C
368 lines
8.6 KiB
C
/*
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* linux/arch/kernel/time-ts.c
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*
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* Based on arm clockevents implementation and old bfin time tick.
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*
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* Copyright(C) 2008, GeoTechnologies, Vitja Makarov
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*
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* This code is licenced under the GPL version 2. For details see
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* kernel-base/COPYING.
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*/
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#include <linux/module.h>
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#include <linux/profile.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/irq.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cpufreq.h>
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#include <asm/blackfin.h>
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#include <asm/time.h>
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#include <asm/gptimers.h>
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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/* Accelerators for sched_clock()
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* convert from cycles(64bits) => nanoseconds (64bits)
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* basic equation:
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* ns = cycles / (freq / ns_per_sec)
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* ns = cycles * (ns_per_sec / freq)
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* ns = cycles * (10^9 / (cpu_khz * 10^3))
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* ns = cycles * (10^6 / cpu_khz)
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*
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* Then we use scaling math (suggested by george@mvista.com) to get:
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* ns = cycles * (10^6 * SC / cpu_khz) / SC
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* ns = cycles * cyc2ns_scale / SC
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*
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* And since SC is a constant power of two, we can convert the div
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* into a shift.
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*
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* We can use khz divisor instead of mhz to keep a better precision, since
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* cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
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* (mathieu.desnoyers@polymtl.ca)
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*
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* -johnstul@us.ibm.com "math is hard, lets go shopping!"
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*/
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static unsigned long cyc2ns_scale;
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#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
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static inline void set_cyc2ns_scale(unsigned long cpu_khz)
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{
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cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR) / cpu_khz;
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}
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static inline unsigned long long cycles_2_ns(cycle_t cyc)
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{
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return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
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}
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static cycle_t bfin_read_cycles(struct clocksource *cs)
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{
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return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
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}
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static struct clocksource bfin_cs_cycles = {
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.name = "bfin_cs_cycles",
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.rating = 350,
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.read = bfin_read_cycles,
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.mask = CLOCKSOURCE_MASK(64),
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.shift = 22,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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unsigned long long sched_clock(void)
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{
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return cycles_2_ns(bfin_read_cycles(&bfin_cs_cycles));
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}
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static int __init bfin_cs_cycles_init(void)
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{
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set_cyc2ns_scale(get_cclk() / 1000);
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bfin_cs_cycles.mult = \
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clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift);
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if (clocksource_register(&bfin_cs_cycles))
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panic("failed to register clocksource");
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return 0;
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}
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#else
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# define bfin_cs_cycles_init()
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#endif
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#ifdef CONFIG_GPTMR0_CLOCKSOURCE
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void __init setup_gptimer0(void)
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{
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disable_gptimers(TIMER0bit);
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set_gptimer_config(TIMER0_id, \
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TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
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set_gptimer_period(TIMER0_id, -1);
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set_gptimer_pwidth(TIMER0_id, -2);
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SSYNC();
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enable_gptimers(TIMER0bit);
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}
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static cycle_t bfin_read_gptimer0(void)
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{
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return bfin_read_TIMER0_COUNTER();
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}
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static struct clocksource bfin_cs_gptimer0 = {
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.name = "bfin_cs_gptimer0",
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.rating = 400,
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.read = bfin_read_gptimer0,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 22,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init bfin_cs_gptimer0_init(void)
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{
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setup_gptimer0();
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bfin_cs_gptimer0.mult = \
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clocksource_hz2mult(get_sclk(), bfin_cs_gptimer0.shift);
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if (clocksource_register(&bfin_cs_gptimer0))
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panic("failed to register clocksource");
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return 0;
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}
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#else
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# define bfin_cs_gptimer0_init()
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#endif
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#ifdef CONFIG_CORE_TIMER_IRQ_L1
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__attribute__((l1_text))
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#endif
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irqreturn_t timer_interrupt(int irq, void *dev_id);
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static int bfin_timer_set_next_event(unsigned long, \
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struct clock_event_device *);
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static void bfin_timer_set_mode(enum clock_event_mode, \
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struct clock_event_device *);
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static struct clock_event_device clockevent_bfin = {
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#if defined(CONFIG_TICKSOURCE_GPTMR0)
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.name = "bfin_gptimer0",
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.rating = 300,
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.irq = IRQ_TIMER0,
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#else
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.name = "bfin_core_timer",
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.rating = 350,
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.irq = IRQ_CORETMR,
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#endif
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.shift = 32,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = bfin_timer_set_next_event,
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.set_mode = bfin_timer_set_mode,
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};
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static struct irqaction bfin_timer_irq = {
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#if defined(CONFIG_TICKSOURCE_GPTMR0)
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.name = "Blackfin GPTimer0",
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#else
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.name = "Blackfin CoreTimer",
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#endif
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.flags = IRQF_DISABLED | IRQF_TIMER | \
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IRQF_IRQPOLL | IRQF_PERCPU,
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.handler = timer_interrupt,
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.dev_id = &clockevent_bfin,
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};
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#if defined(CONFIG_TICKSOURCE_GPTMR0)
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static int bfin_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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disable_gptimers(TIMER0bit);
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/* it starts counting three SCLK cycles after the TIMENx bit is set */
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set_gptimer_pwidth(TIMER0_id, cycles - 3);
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enable_gptimers(TIMER0bit);
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return 0;
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}
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static void bfin_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC: {
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set_gptimer_config(TIMER0_id, \
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TIMER_OUT_DIS | TIMER_IRQ_ENA | \
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TIMER_PERIOD_CNT | TIMER_MODE_PWM);
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set_gptimer_period(TIMER0_id, get_sclk() / HZ);
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set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
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enable_gptimers(TIMER0bit);
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break;
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}
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case CLOCK_EVT_MODE_ONESHOT:
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disable_gptimers(TIMER0bit);
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set_gptimer_config(TIMER0_id, \
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TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
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set_gptimer_period(TIMER0_id, 0);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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disable_gptimers(TIMER0bit);
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break;
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static void bfin_timer_ack(void)
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{
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set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0);
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}
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static void __init bfin_timer_init(void)
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{
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disable_gptimers(TIMER0bit);
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}
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static unsigned long __init bfin_clockevent_check(void)
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{
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setup_irq(IRQ_TIMER0, &bfin_timer_irq);
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return get_sclk();
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}
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#else /* CONFIG_TICKSOURCE_CORETMR */
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static int bfin_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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bfin_write_TCNTL(TMPWR);
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CSYNC();
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bfin_write_TCOUNT(cycles);
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CSYNC();
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bfin_write_TCNTL(TMPWR | TMREN);
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return 0;
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}
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static void bfin_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC: {
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unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
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bfin_write_TCNTL(TMPWR);
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CSYNC();
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bfin_write_TSCALE(TIME_SCALE - 1);
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bfin_write_TPERIOD(tcount);
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bfin_write_TCOUNT(tcount);
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CSYNC();
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bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
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break;
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}
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case CLOCK_EVT_MODE_ONESHOT:
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bfin_write_TCNTL(TMPWR);
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CSYNC();
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bfin_write_TSCALE(TIME_SCALE - 1);
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bfin_write_TPERIOD(0);
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bfin_write_TCOUNT(0);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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bfin_write_TCNTL(0);
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CSYNC();
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break;
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static void bfin_timer_ack(void)
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{
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}
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static void __init bfin_timer_init(void)
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{
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/* power up the timer, but don't enable it just yet */
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bfin_write_TCNTL(TMPWR);
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CSYNC();
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/*
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* the TSCALE prescaler counter.
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*/
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bfin_write_TSCALE(TIME_SCALE - 1);
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bfin_write_TPERIOD(0);
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bfin_write_TCOUNT(0);
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CSYNC();
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}
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static unsigned long __init bfin_clockevent_check(void)
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{
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setup_irq(IRQ_CORETMR, &bfin_timer_irq);
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return get_cclk() / TIME_SCALE;
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}
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void __init setup_core_timer(void)
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{
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bfin_timer_init();
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bfin_timer_set_mode(CLOCK_EVT_MODE_PERIODIC, NULL);
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}
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#endif /* CONFIG_TICKSOURCE_GPTMR0 */
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/*
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* timer_interrupt() needs to keep up the real-time clock,
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* as well as call the "do_timer()" routine every clocktick
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*/
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irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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smp_mb();
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evt->event_handler(evt);
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bfin_timer_ack();
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return IRQ_HANDLED;
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}
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static int __init bfin_clockevent_init(void)
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{
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unsigned long timer_clk;
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timer_clk = bfin_clockevent_check();
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bfin_timer_init();
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clockevent_bfin.mult = div_sc(timer_clk, NSEC_PER_SEC, clockevent_bfin.shift);
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clockevent_bfin.max_delta_ns = clockevent_delta2ns(-1, &clockevent_bfin);
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clockevent_bfin.min_delta_ns = clockevent_delta2ns(100, &clockevent_bfin);
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clockevent_bfin.cpumask = cpumask_of(0);
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clockevents_register_device(&clockevent_bfin);
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return 0;
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}
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void __init time_init(void)
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{
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time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
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#ifdef CONFIG_RTC_DRV_BFIN
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/* [#2663] hack to filter junk RTC values that would cause
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* userspace to have to deal with time values greater than
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* 2^31 seconds (which uClibc cannot cope with yet)
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*/
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if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
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printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
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bfin_write_RTC_STAT(0);
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}
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#endif
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/* Initialize xtime. From now on, xtime is updated with timer interrupts */
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xtime.tv_sec = secs_since_1970;
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xtime.tv_nsec = 0;
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set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
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bfin_cs_cycles_init();
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bfin_cs_gptimer0_init();
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bfin_clockevent_init();
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}
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