2c0b8a7578
Actually, on 386, cmpxchg and cmpxchg_local fall back on cmpxchg_386_u8/16/32: it disables interruptions around non atomic updates to mimic the cmpxchg behavior. The comment: /* Poor man's cmpxchg for 386. Unsuitable for SMP */ already present in cmpxchg_386_u32 tells much about how this cmpxchg implementation should not be used in a SMP context. However, the cmpxchg_local can perfectly use this fallback, since it only needs to be atomic wrt the local cpu. This patch adds a cmpxchg_486_u64 and uses it as a fallback for cmpxchg64 and cmpxchg64_local on 80386 and 80486. Q: but why is it called cmpxchg_486 when the other functions are called A: Because the standard cmpxchg is missing only on 386, but cmpxchg8b is missing both on 386 and 486. Citing Intel's Instruction set reference: cmpxchg: This instruction is not supported on Intel processors earlier than the Intel486 processors. cmpxchg8b: This instruction encoding is not supported on Intel processors earlier than the Pentium processors. Q: What's the reason to have cmpxchg64_local on 32 bit architectures? Without that need all this would just be a few simple defines. A: cmpxchg64_local on 32 bits architectures takes unsigned long long parameters, but cmpxchg_local only takes longs. Since we have cmpxchg8b to execute a 8 byte cmpxchg atomically on pentium and +, it makes sense to provide a flavor of cmpxchg and cmpxchg_local using this instruction. Also, for 32 bits architectures lacking the 64 bits atomic cmpxchg, it makes sense _not_ to define cmpxchg64 while cmpxchg could still be available. Moreover, the fallback for cmpxchg8b on i386 for 386 and 486 is a However, cmpxchg64_local will be emulated by disabling interrupts on all architectures where it is not supported atomically. Therefore, we *could* turn cmpxchg64_local into a cmpxchg_local, but it would make the 386/486 fallbacks ugly, make its design different from cmpxchg/cmpxchg64 (which really depends on atomic operations and cannot be emulated) and require the __cmpxchg_local to be expressed as a macro rather than an inline function so the parameters would not be fixed to unsigned long long in every case. So I think cmpxchg64_local makes sense there, but I am open to suggestions. Q: Are there any callers? A: I am actually using it in LTTng in my timestamping code. I use it to work around CPUs with asynchronous TSCs. I need to update 64 bits values atomically on this 32 bits architecture. Changelog: - Ran though checkpatch. Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
326 lines
8.9 KiB
C
326 lines
8.9 KiB
C
#ifndef __ASM_CMPXCHG_H
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#define __ASM_CMPXCHG_H
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#include <linux/bitops.h> /* for LOCK_PREFIX */
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/*
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* Note: if you use set64_bit(), __cmpxchg64(), or their variants, you
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* you need to test for the feature in boot_cpu_data.
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*/
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#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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/*
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* The semantics of XCHGCMP8B are a bit strange, this is why
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* there is a loop and the loading of %%eax and %%edx has to
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* be inside. This inlines well in most cases, the cached
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* cost is around ~38 cycles. (in the future we might want
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* to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
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* might have an implicit FPU-save as a cost, so it's not
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* clear which path to go.)
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*
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* cmpxchg8b must be used with the lock prefix here to allow
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* the instruction to be executed atomically, see page 3-102
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* of the instruction set reference 24319102.pdf. We need
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* the reader side to see the coherent 64bit value.
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*/
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static inline void __set_64bit (unsigned long long * ptr,
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unsigned int low, unsigned int high)
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{
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__asm__ __volatile__ (
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"\n1:\t"
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"movl (%0), %%eax\n\t"
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"movl 4(%0), %%edx\n\t"
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LOCK_PREFIX "cmpxchg8b (%0)\n\t"
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"jnz 1b"
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: /* no outputs */
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: "D"(ptr),
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"b"(low),
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"c"(high)
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: "ax","dx","memory");
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}
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static inline void __set_64bit_constant (unsigned long long *ptr,
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unsigned long long value)
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{
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__set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
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}
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#define ll_low(x) *(((unsigned int*)&(x))+0)
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#define ll_high(x) *(((unsigned int*)&(x))+1)
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static inline void __set_64bit_var (unsigned long long *ptr,
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unsigned long long value)
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{
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__set_64bit(ptr,ll_low(value), ll_high(value));
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}
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#define set_64bit(ptr,value) \
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(__builtin_constant_p(value) ? \
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__set_64bit_constant(ptr, value) : \
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__set_64bit_var(ptr, value) )
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#define _set_64bit(ptr,value) \
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(__builtin_constant_p(value) ? \
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__set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
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__set_64bit(ptr, ll_low(value), ll_high(value)) )
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument. --ANK
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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:"=q" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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}
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return x;
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}
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#ifdef CONFIG_X86_CMPXCHG
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#define __HAVE_ARCH_CMPXCHG 1
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#define cmpxchg(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))))
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#define sync_cmpxchg(ptr, o, n) \
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((__typeof__(*(ptr)))__sync_cmpxchg((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))))
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#define cmpxchg_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))))
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#endif
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#ifdef CONFIG_X86_CMPXCHG64
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#define cmpxchg64(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg64((ptr), (unsigned long long)(o), \
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(unsigned long long)(n)))
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#define cmpxchg64_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg64_local((ptr), (unsigned long long)(o),\
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(unsigned long long)(n)))
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#endif
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static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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unsigned long prev;
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switch (size) {
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case 1:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 2:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 4:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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}
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return old;
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}
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/*
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* Always use locked operations when touching memory shared with a
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* hypervisor, since the system may be SMP even if the guest kernel
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* isn't.
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*/
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static inline unsigned long __sync_cmpxchg(volatile void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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unsigned long prev;
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switch (size) {
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case 1:
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__asm__ __volatile__("lock; cmpxchgb %b1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 2:
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__asm__ __volatile__("lock; cmpxchgw %w1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 4:
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__asm__ __volatile__("lock; cmpxchgl %1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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}
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return old;
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}
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static inline unsigned long __cmpxchg_local(volatile void *ptr,
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unsigned long old, unsigned long new, int size)
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{
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unsigned long prev;
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switch (size) {
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case 1:
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__asm__ __volatile__("cmpxchgb %b1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 2:
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__asm__ __volatile__("cmpxchgw %w1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 4:
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__asm__ __volatile__("cmpxchgl %1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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}
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return old;
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}
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static inline unsigned long long __cmpxchg64(volatile void *ptr,
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unsigned long long old, unsigned long long new)
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{
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unsigned long long prev;
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__asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
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: "=A"(prev)
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: "b"((unsigned long)new),
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"c"((unsigned long)(new >> 32)),
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"m"(*__xg(ptr)),
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"0"(old)
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: "memory");
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return prev;
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}
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static inline unsigned long long __cmpxchg64_local(volatile void *ptr,
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unsigned long long old, unsigned long long new)
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{
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unsigned long long prev;
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__asm__ __volatile__("cmpxchg8b %3"
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: "=A"(prev)
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: "b"((unsigned long)new),
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"c"((unsigned long)(new >> 32)),
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"m"(*__xg(ptr)),
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"0"(old)
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: "memory");
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return prev;
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}
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#ifndef CONFIG_X86_CMPXCHG
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/*
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* Building a kernel capable running on 80386. It may be necessary to
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* simulate the cmpxchg on the 80386 CPU. For that purpose we define
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* a function for each of the sizes we support.
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*/
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extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
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extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
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extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
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static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 1:
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return cmpxchg_386_u8(ptr, old, new);
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case 2:
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return cmpxchg_386_u16(ptr, old, new);
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case 4:
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return cmpxchg_386_u32(ptr, old, new);
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}
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return old;
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}
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#define cmpxchg(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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if (likely(boot_cpu_data.x86 > 3)) \
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__ret = __cmpxchg((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))); \
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else \
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__ret = cmpxchg_386((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))); \
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__ret; \
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})
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#define cmpxchg_local(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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if (likely(boot_cpu_data.x86 > 3)) \
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__ret = __cmpxchg_local((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))); \
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else \
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__ret = cmpxchg_386((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))); \
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__ret; \
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})
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#endif
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#ifndef CONFIG_X86_CMPXCHG64
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/*
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* Building a kernel capable running on 80386 and 80486. It may be necessary
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* to simulate the cmpxchg8b on the 80386 and 80486 CPU.
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*/
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extern unsigned long long cmpxchg_486_u64(volatile void *, u64, u64);
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#define cmpxchg64(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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if (likely(boot_cpu_data.x86 > 4)) \
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__ret = __cmpxchg64((ptr), (unsigned long long)(o), \
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(unsigned long long)(n)); \
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else \
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__ret = cmpxchg_486_u64((ptr), (unsigned long long)(o), \
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(unsigned long long)(n)); \
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__ret; \
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})
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#define cmpxchg64_local(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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if (likely(boot_cpu_data.x86 > 4)) \
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__ret = __cmpxchg64_local((ptr), (unsigned long long)(o), \
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(unsigned long long)(n)); \
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else \
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__ret = cmpxchg_486_u64((ptr), (unsigned long long)(o), \
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(unsigned long long)(n)); \
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__ret; \
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})
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#endif
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#endif
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