fac23fe4be
The current feature section logic only supports nop'ing out code, this means if you want to choose at runtime between instruction sequences, one or both cases will have to execute the nop'ed out contents of the other section, eg: BEGIN_FTR_SECTION or 1,1,1 END_FTR_SECTION_IFSET(FOO) BEGIN_FTR_SECTION or 2,2,2 END_FTR_SECTION_IFCLR(FOO) and the resulting code will be either, or 1,1,1 nop or, nop or 2,2,2 For small code segments this is fine, but for larger code blocks and in performance criticial code segments, it would be nice to avoid the nops. This commit starts to implement logic to allow the following: BEGIN_FTR_SECTION or 1,1,1 FTR_SECTION_ELSE or 2,2,2 ALT_FTR_SECTION_END_IFSET(FOO) and the resulting code will be: or 1,1,1 or, or 2,2,2 We achieve this by extending the existing FTR macros. The current feature section semantic just becomes a special case, ie. if the else case is empty we nop out the default case. The key limitation is that the size of the else case must be less than or equal to the size of the default case. If the else case is smaller the remainder of the section is nop'ed. We let the linker put the else case code in with the rest of the text, so that relative branches from the else case are more likley to link, this has the disadvantage that we can't free the unused else cases. This commit introduces the required macro and linker script changes, but does not enable the patching of the alternative sections. We also need to update two hand-made section entries in reg.h and timex.h Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
51 lines
823 B
C
51 lines
823 B
C
#ifndef _ASM_POWERPC_TIMEX_H
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#define _ASM_POWERPC_TIMEX_H
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#ifdef __KERNEL__
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/*
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* PowerPC architecture timex specifications
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*/
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#include <asm/cputable.h>
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#include <asm/reg.h>
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#define CLOCK_TICK_RATE 1024000 /* Underlying HZ */
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typedef unsigned long cycles_t;
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static inline cycles_t get_cycles(void)
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{
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#ifdef __powerpc64__
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return mftb();
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#else
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cycles_t ret;
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/*
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* For the "cycle" counter we use the timebase lower half.
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* Currently only used on SMP.
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*/
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ret = 0;
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__asm__ __volatile__(
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"97: mftb %0\n"
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"99:\n"
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".section __ftr_fixup,\"a\"\n"
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".align 2\n"
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"98:\n"
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" .long %1\n"
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" .long 0\n"
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" .long 97b-98b\n"
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" .long 99b-98b\n"
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" .long 0\n"
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" .long 0\n"
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".previous"
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: "=r" (ret) : "i" (CPU_FTR_601));
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return ret;
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#endif
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_TIMEX_H */
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