6eb5d146d4
Before it isn't too late let's switch to IO memory accessors. This patch converts all current _REG users and _REG definitions. There should be no functional changes. Suggested-by: Ben Dooks <ben-linux@fluff.org> Suggested-by: Sergei Shtylyov <sshtylyov@mvista.com> Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
102 lines
2.2 KiB
C
102 lines
2.2 KiB
C
/*
|
|
* Copyright 2008 Cavium Networks
|
|
*
|
|
* This file is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License, Version 2, as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <linux/io.h>
|
|
#include <linux/delay.h>
|
|
#include <mach/system.h>
|
|
#include <mach/cns3xxx.h>
|
|
|
|
void cns3xxx_pwr_clk_en(unsigned int block)
|
|
{
|
|
u32 reg = __raw_readl(PM_CLK_GATE_REG);
|
|
|
|
reg |= (block & PM_CLK_GATE_REG_MASK);
|
|
__raw_writel(reg, PM_CLK_GATE_REG);
|
|
}
|
|
|
|
void cns3xxx_pwr_power_up(unsigned int block)
|
|
{
|
|
u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
|
|
|
|
reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
|
|
__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
|
|
|
|
/* Wait for 300us for the PLL output clock locked. */
|
|
udelay(300);
|
|
};
|
|
|
|
void cns3xxx_pwr_power_down(unsigned int block)
|
|
{
|
|
u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
|
|
|
|
/* write '1' to power down */
|
|
reg |= (block & CNS3XXX_PWR_PLL_ALL);
|
|
__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
|
|
};
|
|
|
|
static void cns3xxx_pwr_soft_rst_force(unsigned int block)
|
|
{
|
|
u32 reg = __raw_readl(PM_SOFT_RST_REG);
|
|
|
|
/*
|
|
* bit 0, 28, 29 => program low to reset,
|
|
* the other else program low and then high
|
|
*/
|
|
if (block & 0x30000001) {
|
|
reg &= ~(block & PM_SOFT_RST_REG_MASK);
|
|
} else {
|
|
reg &= ~(block & PM_SOFT_RST_REG_MASK);
|
|
reg |= (block & PM_SOFT_RST_REG_MASK);
|
|
}
|
|
|
|
__raw_writel(reg, PM_SOFT_RST_REG);
|
|
}
|
|
|
|
void cns3xxx_pwr_soft_rst(unsigned int block)
|
|
{
|
|
static unsigned int soft_reset;
|
|
|
|
if (soft_reset & block) {
|
|
/* SPI/I2C/GPIO use the same block, reset once. */
|
|
return;
|
|
} else {
|
|
soft_reset |= block;
|
|
}
|
|
cns3xxx_pwr_soft_rst_force(block);
|
|
}
|
|
|
|
void arch_reset(char mode, const char *cmd)
|
|
{
|
|
/*
|
|
* To reset, we hit the on-board reset register
|
|
* in the system FPGA.
|
|
*/
|
|
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
|
|
}
|
|
|
|
/*
|
|
* cns3xxx_cpu_clock - return CPU/L2 clock
|
|
* aclk: cpu clock/2
|
|
* hclk: cpu clock/4
|
|
* pclk: cpu clock/8
|
|
*/
|
|
int cns3xxx_cpu_clock(void)
|
|
{
|
|
u32 reg = __raw_readl(PM_CLK_CTRL_REG);
|
|
int cpu;
|
|
int cpu_sel;
|
|
int div_sel;
|
|
|
|
cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
|
|
div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
|
|
|
|
cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
|
|
|
|
return cpu;
|
|
}
|