6b7d815c3f
mxs_reset_block() clears the PIO_QUEUE_MODE bit. So we have to set it again after a controller reset. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
413 lines
10 KiB
C
413 lines
10 KiB
C
/*
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* Freescale MXS I2C bus driver
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*
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* Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
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*
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* based on a (non-working) driver which was:
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*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* TODO: add dma-support if platform-support for it is available
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/completion.h>
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#include <linux/platform_device.h>
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#include <linux/jiffies.h>
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#include <linux/io.h>
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#include <mach/common.h>
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#define DRIVER_NAME "mxs-i2c"
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#define MXS_I2C_CTRL0 (0x00)
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#define MXS_I2C_CTRL0_SET (0x04)
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#define MXS_I2C_CTRL0_SFTRST 0x80000000
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#define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
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#define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
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#define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
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#define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
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#define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
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#define MXS_I2C_CTRL0_DIRECTION 0x00010000
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#define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
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#define MXS_I2C_CTRL1 (0x40)
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#define MXS_I2C_CTRL1_SET (0x44)
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#define MXS_I2C_CTRL1_CLR (0x48)
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#define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
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#define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
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#define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
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#define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
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#define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
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#define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
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#define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
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#define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
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#define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
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MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
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MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
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MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
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MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
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MXS_I2C_CTRL1_SLAVE_IRQ)
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#define MXS_I2C_QUEUECTRL (0x60)
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#define MXS_I2C_QUEUECTRL_SET (0x64)
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#define MXS_I2C_QUEUECTRL_CLR (0x68)
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#define MXS_I2C_QUEUECTRL_QUEUE_RUN 0x20
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#define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE 0x04
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#define MXS_I2C_QUEUESTAT (0x70)
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#define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000
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#define MXS_I2C_QUEUECMD (0x80)
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#define MXS_I2C_QUEUEDATA (0x90)
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#define MXS_I2C_DATA (0xa0)
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#define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
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MXS_I2C_CTRL0_PRE_SEND_START | \
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MXS_I2C_CTRL0_MASTER_MODE | \
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MXS_I2C_CTRL0_DIRECTION | \
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MXS_I2C_CTRL0_XFER_COUNT(1))
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#define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
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MXS_I2C_CTRL0_MASTER_MODE | \
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MXS_I2C_CTRL0_DIRECTION)
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#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
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MXS_I2C_CTRL0_MASTER_MODE)
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/**
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* struct mxs_i2c_dev - per device, private MXS-I2C data
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*
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* @dev: driver model device node
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* @regs: IO registers pointer
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* @cmd_complete: completion object for transaction wait
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* @cmd_err: error code for last transaction
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* @adapter: i2c subsystem adapter node
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*/
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struct mxs_i2c_dev {
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struct device *dev;
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void __iomem *regs;
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struct completion cmd_complete;
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u32 cmd_err;
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struct i2c_adapter adapter;
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};
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/*
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* TODO: check if calls to here are really needed. If not, we could get rid of
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* mxs_reset_block and the mach-dependency. Needs an I2C analyzer, probably.
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*/
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static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
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{
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mxs_reset_block(i2c->regs);
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writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
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writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
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i2c->regs + MXS_I2C_QUEUECTRL_SET);
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}
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static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len,
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int flags)
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{
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u32 data;
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writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD);
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data = (addr << 1) | I2C_SMBUS_READ;
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writel(data, i2c->regs + MXS_I2C_DATA);
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data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags;
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writel(data, i2c->regs + MXS_I2C_QUEUECMD);
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}
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static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c,
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u8 addr, u8 *buf, int len, int flags)
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{
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u32 data;
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int i, shifts_left;
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data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags;
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writel(data, i2c->regs + MXS_I2C_QUEUECMD);
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/*
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* We have to copy the slave address (u8) and buffer (arbitrary number
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* of u8) into the data register (u32). To achieve that, the u8 are put
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* into the MSBs of 'data' which is then shifted for the next u8. When
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* apropriate, 'data' is written to MXS_I2C_DATA. So, the first u32
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* looks like this:
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*
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* 3 2 1 0
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* 10987654|32109876|54321098|76543210
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* --------+--------+--------+--------
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* buffer+2|buffer+1|buffer+0|slave_addr
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*/
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data = ((addr << 1) | I2C_SMBUS_WRITE) << 24;
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for (i = 0; i < len; i++) {
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data >>= 8;
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data |= buf[i] << 24;
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if ((i & 3) == 2)
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writel(data, i2c->regs + MXS_I2C_DATA);
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}
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/* Write out the remaining bytes if any */
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shifts_left = 24 - (i & 3) * 8;
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if (shifts_left)
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writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA);
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}
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/*
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* TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the
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* rd_threshold to 1). Couldn't get this to work, though.
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*/
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static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(1000);
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while (readl(i2c->regs + MXS_I2C_QUEUESTAT)
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& MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) {
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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cond_resched();
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}
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return 0;
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}
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static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len)
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{
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u32 data;
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int i;
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for (i = 0; i < len; i++) {
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if ((i & 3) == 0) {
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if (mxs_i2c_wait_for_data(i2c))
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return -ETIMEDOUT;
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data = readl(i2c->regs + MXS_I2C_QUEUEDATA);
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}
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buf[i] = data & 0xff;
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data >>= 8;
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}
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return 0;
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}
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/*
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* Low level master read/write transaction.
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*/
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static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
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int stop)
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{
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struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
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int ret;
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int flags;
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init_completion(&i2c->cmd_complete);
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dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
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msg->addr, msg->len, msg->flags, stop);
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if (msg->len == 0)
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return -EINVAL;
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flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
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if (msg->flags & I2C_M_RD)
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mxs_i2c_pioq_setup_read(i2c, msg->addr, msg->len, flags);
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else
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mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, msg->len,
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flags);
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writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
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i2c->regs + MXS_I2C_QUEUECTRL_SET);
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ret = wait_for_completion_timeout(&i2c->cmd_complete,
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msecs_to_jiffies(1000));
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if (ret == 0)
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goto timeout;
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if ((!i2c->cmd_err) && (msg->flags & I2C_M_RD)) {
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ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len);
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if (ret)
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goto timeout;
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}
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if (i2c->cmd_err == -ENXIO)
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mxs_i2c_reset(i2c);
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dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
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return i2c->cmd_err;
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timeout:
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dev_dbg(i2c->dev, "Timeout!\n");
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mxs_i2c_reset(i2c);
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return -ETIMEDOUT;
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}
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static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
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int num)
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{
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int i;
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int err;
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for (i = 0; i < num; i++) {
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err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
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if (err)
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return err;
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}
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return num;
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}
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static u32 mxs_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
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}
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static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
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{
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struct mxs_i2c_dev *i2c = dev_id;
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u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
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if (!stat)
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return IRQ_NONE;
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if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
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i2c->cmd_err = -ENXIO;
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else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
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MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
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MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
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/* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
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i2c->cmd_err = -EIO;
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else
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i2c->cmd_err = 0;
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complete(&i2c->cmd_complete);
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writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
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return IRQ_HANDLED;
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}
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static const struct i2c_algorithm mxs_i2c_algo = {
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.master_xfer = mxs_i2c_xfer,
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.functionality = mxs_i2c_func,
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};
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static int __devinit mxs_i2c_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mxs_i2c_dev *i2c;
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struct i2c_adapter *adap;
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struct resource *res;
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resource_size_t res_size;
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int err, irq;
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i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
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if (!i2c)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENOENT;
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res_size = resource_size(res);
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if (!devm_request_mem_region(dev, res->start, res_size, res->name))
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return -EBUSY;
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i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
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if (!i2c->regs)
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return -EBUSY;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
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if (err)
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return err;
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i2c->dev = dev;
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platform_set_drvdata(pdev, i2c);
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/* Do reset to enforce correct startup after pinmuxing */
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mxs_i2c_reset(i2c);
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adap = &i2c->adapter;
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strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
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adap->owner = THIS_MODULE;
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adap->algo = &mxs_i2c_algo;
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adap->dev.parent = dev;
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adap->nr = pdev->id;
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i2c_set_adapdata(adap, i2c);
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err = i2c_add_numbered_adapter(adap);
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if (err) {
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dev_err(dev, "Failed to add adapter (%d)\n", err);
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writel(MXS_I2C_CTRL0_SFTRST,
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i2c->regs + MXS_I2C_CTRL0_SET);
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return err;
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}
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return 0;
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}
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static int __devexit mxs_i2c_remove(struct platform_device *pdev)
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{
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struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
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int ret;
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ret = i2c_del_adapter(&i2c->adapter);
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if (ret)
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return -EBUSY;
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writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
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i2c->regs + MXS_I2C_QUEUECTRL_CLR);
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writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver mxs_i2c_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.owner = THIS_MODULE,
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},
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.remove = __devexit_p(mxs_i2c_remove),
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};
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static int __init mxs_i2c_init(void)
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{
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return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
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}
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subsys_initcall(mxs_i2c_init);
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static void __exit mxs_i2c_exit(void)
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{
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platform_driver_unregister(&mxs_i2c_driver);
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}
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module_exit(mxs_i2c_exit);
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MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
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MODULE_DESCRIPTION("MXS I2C Bus Driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:" DRIVER_NAME);
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