285f5fa7e9
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
25 lines
455 B
C
25 lines
455 B
C
#include <asm/types.h>
|
|
#include <linux/serial_reg.h>
|
|
#include <asm/hardware.h>
|
|
#include <asm/processor.h>
|
|
|
|
#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
|
|
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
|
|
|
|
static inline void putc(char c)
|
|
{
|
|
while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
|
|
cpu_relax();
|
|
UART_BASE[UART_TX] = c;
|
|
}
|
|
|
|
static inline void flush(void)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* nothing to do
|
|
*/
|
|
#define arch_decomp_setup()
|
|
#define arch_decomp_wdog()
|