c5a89c6c08
The at91 mci controller internal state machine seems to often crash. This can be fixed by resetting the controller after each command for at91rm9200 and by setting the MCI_BLKR register on at91sam926*. Signed-off-by: Marc Pignat <marc.pignat@hevs.ch> Signed-off-by: Hans J Koch <hjk@linutronix.de> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
114 lines
5.1 KiB
C
114 lines
5.1 KiB
C
/*
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* include/asm-arm/arch-at91/at91_mci.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* MultiMedia Card Interface (MCI) registers.
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* Based on AT91RM9200 datasheet revision F.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_MCI_H
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#define AT91_MCI_H
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#define AT91_MCI_CR 0x00 /* Control Register */
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#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
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#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
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#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */
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#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */
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#define AT91_MCI_SWRST (1 << 7) /* Software Reset */
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#define AT91_MCI_MR 0x04 /* Mode Register */
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#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
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#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
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#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
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#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
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#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
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#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
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#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
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#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
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#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
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#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
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#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */
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#define AT91_MCI_DTOMUL_1 (0 << 4)
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#define AT91_MCI_DTOMUL_16 (1 << 4)
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#define AT91_MCI_DTOMUL_128 (2 << 4)
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#define AT91_MCI_DTOMUL_256 (3 << 4)
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#define AT91_MCI_DTOMUL_1K (4 << 4)
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#define AT91_MCI_DTOMUL_4K (5 << 4)
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#define AT91_MCI_DTOMUL_64K (6 << 4)
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#define AT91_MCI_DTOMUL_1M (7 << 4)
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#define AT91_MCI_SDCR 0x0c /* SD Card Register */
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#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
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#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
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#define AT91_MCI_ARGR 0x10 /* Argument Register */
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#define AT91_MCI_CMDR 0x14 /* Command Register */
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#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */
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#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */
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#define AT91_MCI_RSPTYP_NONE (0 << 6)
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#define AT91_MCI_RSPTYP_48 (1 << 6)
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#define AT91_MCI_RSPTYP_136 (2 << 6)
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#define AT91_MCI_SPCMD (7 << 8) /* Special Command */
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#define AT91_MCI_SPCMD_NONE (0 << 8)
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#define AT91_MCI_SPCMD_INIT (1 << 8)
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#define AT91_MCI_SPCMD_SYNC (2 << 8)
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#define AT91_MCI_SPCMD_ICMD (4 << 8)
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#define AT91_MCI_SPCMD_IRESP (5 << 8)
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#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */
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#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */
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#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */
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#define AT91_MCI_TRCMD_NONE (0 << 16)
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#define AT91_MCI_TRCMD_START (1 << 16)
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#define AT91_MCI_TRCMD_STOP (2 << 16)
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#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */
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#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */
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#define AT91_MCI_TRTYP_BLOCK (0 << 19)
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#define AT91_MCI_TRTYP_MULTIPLE (1 << 19)
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#define AT91_MCI_TRTYP_STREAM (2 << 19)
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#define AT91_MCI_BLKR 0x18 /* Block Register */
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#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */
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#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */
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#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
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#define AT91_MCR_RDR 0x30 /* Receive Data Register */
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#define AT91_MCR_TDR 0x34 /* Transmit Data Register */
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#define AT91_MCI_SR 0x40 /* Status Register */
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#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */
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#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
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#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */
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#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */
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#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */
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#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */
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#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
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#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
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#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
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#define AT91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B */
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#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
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#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
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#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
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#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */
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#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
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#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */
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#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */
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#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */
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#define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */
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#define AT91_MCI_OVRE (1 << 30) /* Overrun */
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#define AT91_MCI_UNRE (1 << 31) /* Underrun */
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#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */
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#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */
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#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */
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#endif
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