e30af4ce7f
mmio.c includes mmio decoder, and related mmio logics. Signed-off-by: Anthony Xu <Anthony.xu@intel.com> Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
342 lines
8.5 KiB
C
342 lines
8.5 KiB
C
/*
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* mmio.c: MMIO emulation components.
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* Copyright (c) 2004, Intel Corporation.
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* Yaozu Dong (Eddie Dong) (Eddie.dong@intel.com)
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* Kun Tian (Kevin Tian) (Kevin.tian@intel.com)
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*
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* Copyright (c) 2007 Intel Corporation KVM support.
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* Xuefei Xu (Anthony Xu) (anthony.xu@intel.com)
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* Xiantao Zhang (xiantao.zhang@intel.com)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <linux/kvm_host.h>
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#include "vcpu.h"
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static void vlsapic_write_xtp(struct kvm_vcpu *v, uint8_t val)
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{
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VLSAPIC_XTP(v) = val;
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}
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/*
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* LSAPIC OFFSET
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*/
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#define PIB_LOW_HALF(ofst) !(ofst & (1 << 20))
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#define PIB_OFST_INTA 0x1E0000
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#define PIB_OFST_XTP 0x1E0008
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/*
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* execute write IPI op.
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*/
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static void vlsapic_write_ipi(struct kvm_vcpu *vcpu,
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uint64_t addr, uint64_t data)
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{
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struct exit_ctl_data *p = ¤t_vcpu->arch.exit_data;
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unsigned long psr;
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local_irq_save(psr);
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p->exit_reason = EXIT_REASON_IPI;
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p->u.ipi_data.addr.val = addr;
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p->u.ipi_data.data.val = data;
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vmm_transition(current_vcpu);
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local_irq_restore(psr);
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}
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void lsapic_write(struct kvm_vcpu *v, unsigned long addr,
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unsigned long length, unsigned long val)
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{
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addr &= (PIB_SIZE - 1);
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switch (addr) {
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case PIB_OFST_INTA:
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/*panic_domain(NULL, "Undefined write on PIB INTA\n");*/
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panic_vm(v);
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break;
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case PIB_OFST_XTP:
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if (length == 1) {
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vlsapic_write_xtp(v, val);
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} else {
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/*panic_domain(NULL,
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"Undefined write on PIB XTP\n");*/
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panic_vm(v);
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}
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break;
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default:
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if (PIB_LOW_HALF(addr)) {
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/*lower half */
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if (length != 8)
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/*panic_domain(NULL,
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"Can't LHF write with size %ld!\n",
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length);*/
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panic_vm(v);
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else
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vlsapic_write_ipi(v, addr, val);
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} else { /* upper half
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printk("IPI-UHF write %lx\n",addr);*/
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panic_vm(v);
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}
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break;
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}
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}
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unsigned long lsapic_read(struct kvm_vcpu *v, unsigned long addr,
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unsigned long length)
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{
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uint64_t result = 0;
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addr &= (PIB_SIZE - 1);
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switch (addr) {
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case PIB_OFST_INTA:
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if (length == 1) /* 1 byte load */
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; /* There is no i8259, there is no INTA access*/
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else
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/*panic_domain(NULL,"Undefined read on PIB INTA\n"); */
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panic_vm(v);
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break;
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case PIB_OFST_XTP:
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if (length == 1) {
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result = VLSAPIC_XTP(v);
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/* printk("read xtp %lx\n", result); */
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} else {
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/*panic_domain(NULL,
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"Undefined read on PIB XTP\n");*/
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panic_vm(v);
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}
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break;
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default:
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panic_vm(v);
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break;
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}
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return result;
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}
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static void mmio_access(struct kvm_vcpu *vcpu, u64 src_pa, u64 *dest,
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u16 s, int ma, int dir)
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{
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unsigned long iot;
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struct exit_ctl_data *p = &vcpu->arch.exit_data;
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unsigned long psr;
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iot = __gpfn_is_io(src_pa >> PAGE_SHIFT);
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local_irq_save(psr);
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/*Intercept the acces for PIB range*/
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if (iot == GPFN_PIB) {
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if (!dir)
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lsapic_write(vcpu, src_pa, s, *dest);
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else
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*dest = lsapic_read(vcpu, src_pa, s);
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goto out;
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}
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p->exit_reason = EXIT_REASON_MMIO_INSTRUCTION;
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p->u.ioreq.addr = src_pa;
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p->u.ioreq.size = s;
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p->u.ioreq.dir = dir;
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if (dir == IOREQ_WRITE)
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p->u.ioreq.data = *dest;
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p->u.ioreq.state = STATE_IOREQ_READY;
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vmm_transition(vcpu);
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if (p->u.ioreq.state == STATE_IORESP_READY) {
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if (dir == IOREQ_READ)
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*dest = p->u.ioreq.data;
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} else
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panic_vm(vcpu);
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out:
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local_irq_restore(psr);
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return ;
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}
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/*
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dir 1: read 0:write
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inst_type 0:integer 1:floating point
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*/
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#define SL_INTEGER 0 /* store/load interger*/
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#define SL_FLOATING 1 /* store/load floating*/
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void emulate_io_inst(struct kvm_vcpu *vcpu, u64 padr, u64 ma)
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{
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struct kvm_pt_regs *regs;
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IA64_BUNDLE bundle;
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int slot, dir = 0;
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int inst_type = -1;
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u16 size = 0;
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u64 data, slot1a, slot1b, temp, update_reg;
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s32 imm;
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INST64 inst;
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regs = vcpu_regs(vcpu);
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if (fetch_code(vcpu, regs->cr_iip, &bundle)) {
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/* if fetch code fail, return and try again */
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return;
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}
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slot = ((struct ia64_psr *)&(regs->cr_ipsr))->ri;
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if (!slot)
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inst.inst = bundle.slot0;
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else if (slot == 1) {
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slot1a = bundle.slot1a;
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slot1b = bundle.slot1b;
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inst.inst = slot1a + (slot1b << 18);
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} else if (slot == 2)
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inst.inst = bundle.slot2;
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/* Integer Load/Store */
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if (inst.M1.major == 4 && inst.M1.m == 0 && inst.M1.x == 0) {
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inst_type = SL_INTEGER;
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size = (inst.M1.x6 & 0x3);
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if ((inst.M1.x6 >> 2) > 0xb) {
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/*write*/
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dir = IOREQ_WRITE;
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data = vcpu_get_gr(vcpu, inst.M4.r2);
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} else if ((inst.M1.x6 >> 2) < 0xb) {
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/*read*/
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dir = IOREQ_READ;
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}
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} else if (inst.M2.major == 4 && inst.M2.m == 1 && inst.M2.x == 0) {
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/* Integer Load + Reg update */
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inst_type = SL_INTEGER;
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dir = IOREQ_READ;
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size = (inst.M2.x6 & 0x3);
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temp = vcpu_get_gr(vcpu, inst.M2.r3);
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update_reg = vcpu_get_gr(vcpu, inst.M2.r2);
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temp += update_reg;
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vcpu_set_gr(vcpu, inst.M2.r3, temp, 0);
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} else if (inst.M3.major == 5) {
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/*Integer Load/Store + Imm update*/
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inst_type = SL_INTEGER;
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size = (inst.M3.x6&0x3);
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if ((inst.M5.x6 >> 2) > 0xb) {
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/*write*/
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dir = IOREQ_WRITE;
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data = vcpu_get_gr(vcpu, inst.M5.r2);
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temp = vcpu_get_gr(vcpu, inst.M5.r3);
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imm = (inst.M5.s << 31) | (inst.M5.i << 30) |
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(inst.M5.imm7 << 23);
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temp += imm >> 23;
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vcpu_set_gr(vcpu, inst.M5.r3, temp, 0);
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} else if ((inst.M3.x6 >> 2) < 0xb) {
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/*read*/
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dir = IOREQ_READ;
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temp = vcpu_get_gr(vcpu, inst.M3.r3);
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imm = (inst.M3.s << 31) | (inst.M3.i << 30) |
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(inst.M3.imm7 << 23);
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temp += imm >> 23;
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vcpu_set_gr(vcpu, inst.M3.r3, temp, 0);
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}
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} else if (inst.M9.major == 6 && inst.M9.x6 == 0x3B
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&& inst.M9.m == 0 && inst.M9.x == 0) {
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/* Floating-point spill*/
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struct ia64_fpreg v;
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inst_type = SL_FLOATING;
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dir = IOREQ_WRITE;
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vcpu_get_fpreg(vcpu, inst.M9.f2, &v);
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/* Write high word. FIXME: this is a kludge! */
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v.u.bits[1] &= 0x3ffff;
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mmio_access(vcpu, padr + 8, &v.u.bits[1], 8, ma, IOREQ_WRITE);
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data = v.u.bits[0];
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size = 3;
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} else if (inst.M10.major == 7 && inst.M10.x6 == 0x3B) {
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/* Floating-point spill + Imm update */
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struct ia64_fpreg v;
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inst_type = SL_FLOATING;
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dir = IOREQ_WRITE;
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vcpu_get_fpreg(vcpu, inst.M10.f2, &v);
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temp = vcpu_get_gr(vcpu, inst.M10.r3);
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imm = (inst.M10.s << 31) | (inst.M10.i << 30) |
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(inst.M10.imm7 << 23);
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temp += imm >> 23;
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vcpu_set_gr(vcpu, inst.M10.r3, temp, 0);
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/* Write high word.FIXME: this is a kludge! */
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v.u.bits[1] &= 0x3ffff;
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mmio_access(vcpu, padr + 8, &v.u.bits[1], 8, ma, IOREQ_WRITE);
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data = v.u.bits[0];
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size = 3;
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} else if (inst.M10.major == 7 && inst.M10.x6 == 0x31) {
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/* Floating-point stf8 + Imm update */
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struct ia64_fpreg v;
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inst_type = SL_FLOATING;
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dir = IOREQ_WRITE;
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size = 3;
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vcpu_get_fpreg(vcpu, inst.M10.f2, &v);
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data = v.u.bits[0]; /* Significand. */
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temp = vcpu_get_gr(vcpu, inst.M10.r3);
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imm = (inst.M10.s << 31) | (inst.M10.i << 30) |
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(inst.M10.imm7 << 23);
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temp += imm >> 23;
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vcpu_set_gr(vcpu, inst.M10.r3, temp, 0);
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} else if (inst.M15.major == 7 && inst.M15.x6 >= 0x2c
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&& inst.M15.x6 <= 0x2f) {
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temp = vcpu_get_gr(vcpu, inst.M15.r3);
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imm = (inst.M15.s << 31) | (inst.M15.i << 30) |
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(inst.M15.imm7 << 23);
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temp += imm >> 23;
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vcpu_set_gr(vcpu, inst.M15.r3, temp, 0);
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vcpu_increment_iip(vcpu);
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return;
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} else if (inst.M12.major == 6 && inst.M12.m == 1
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&& inst.M12.x == 1 && inst.M12.x6 == 1) {
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/* Floating-point Load Pair + Imm ldfp8 M12*/
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struct ia64_fpreg v;
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inst_type = SL_FLOATING;
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dir = IOREQ_READ;
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size = 8; /*ldfd*/
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mmio_access(vcpu, padr, &data, size, ma, dir);
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v.u.bits[0] = data;
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v.u.bits[1] = 0x1003E;
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vcpu_set_fpreg(vcpu, inst.M12.f1, &v);
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padr += 8;
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mmio_access(vcpu, padr, &data, size, ma, dir);
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v.u.bits[0] = data;
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v.u.bits[1] = 0x1003E;
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vcpu_set_fpreg(vcpu, inst.M12.f2, &v);
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padr += 8;
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vcpu_set_gr(vcpu, inst.M12.r3, padr, 0);
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vcpu_increment_iip(vcpu);
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return;
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} else {
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inst_type = -1;
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panic_vm(vcpu);
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}
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size = 1 << size;
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if (dir == IOREQ_WRITE) {
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mmio_access(vcpu, padr, &data, size, ma, dir);
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} else {
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mmio_access(vcpu, padr, &data, size, ma, dir);
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if (inst_type == SL_INTEGER)
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vcpu_set_gr(vcpu, inst.M1.r1, data, 0);
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else
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panic_vm(vcpu);
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}
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vcpu_increment_iip(vcpu);
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}
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