eca8c24241
The S3C2412 has an reset-errata where the clock may cause a glitch switching back to EXTCLK. We force a switch to EXTCLK before writing the reset register to force use of the CLKCON sync logic to properly switch. Fix problem reported by Matthieu Castet. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
22 lines
607 B
C
22 lines
607 B
C
/* linux/include/asm-arm/arch-s3c2410/regs-s3c2412.h
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*
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* Copyright 2007 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2412 specific register definitions
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*/
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#ifndef __ASM_ARCH_REGS_S3C2412_H
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#define __ASM_ARCH_REGS_S3C2412_H "s3c2412"
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#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30)
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#define S3C2412_SWRST_RESET (0x533C2412)
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#endif /* __ASM_ARCH_REGS_S3C2412_H */
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