e2305e37d4
Needed for LEON AMP systems where different CPUs are routed to different IRQ controllers. This patch selects the IRQ Controller which has been routed to the boot CPU, it is up to the boot loader to configure the IRQ controller. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
264 lines
7.9 KiB
C
264 lines
7.9 KiB
C
/*
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*Copyright (C) 2004 Konrad Eisele (eiselekd@web.de,konrad@gaisler.com), Gaisler Research
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*Copyright (C) 2004 Stefan Holst (mail@s-holst.de), Uni-Stuttgart
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*Copyright (C) 2009 Daniel Hellstrom (daniel@gaisler.com),Konrad Eisele (konrad@gaisler.com) Aeroflex Gaisler AB
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*/
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#ifndef LEON_AMBA_H_INCLUDE
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#define LEON_AMBA_H_INCLUDE
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#ifndef __ASSEMBLY__
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struct amba_prom_registers {
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unsigned int phys_addr; /* The physical address of this register */
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unsigned int reg_size; /* How many bytes does this register take up? */
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};
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#endif
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/*
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* The following defines the bits in the LEON UART Status Registers.
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*/
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#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */
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#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
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#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
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#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */
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#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */
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#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */
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#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */
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#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */
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/*
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* The following defines the bits in the LEON UART Ctrl Registers.
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*/
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#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */
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#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */
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#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */
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#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter irq */
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#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */
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#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */
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#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */
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#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */
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#define LEON3_GPTIMER_EN 1
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#define LEON3_GPTIMER_RL 2
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#define LEON3_GPTIMER_LD 4
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#define LEON3_GPTIMER_IRQEN 8
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#define LEON3_GPTIMER_SEPIRQ 8
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#define LEON23_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */
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/* 0 = hold scalar and counter */
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#define LEON23_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */
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/* 0 = stop at 0 */
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#define LEON23_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */
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/* 0 = no function */
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#define LEON23_REG_TIMER_CONTROL_IQ 0x00000008 /* 1 = irq enable */
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/* 0 = no function */
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/*
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* The following defines the bits in the LEON PS/2 Status Registers.
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*/
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#define LEON_REG_PS2_STATUS_DR 0x00000001 /* Data Ready */
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#define LEON_REG_PS2_STATUS_PE 0x00000002 /* Parity error */
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#define LEON_REG_PS2_STATUS_FE 0x00000004 /* Framing error */
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#define LEON_REG_PS2_STATUS_KI 0x00000008 /* Keyboard inhibit */
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#define LEON_REG_PS2_STATUS_RF 0x00000010 /* RX buffer full */
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#define LEON_REG_PS2_STATUS_TF 0x00000020 /* TX buffer full */
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/*
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* The following defines the bits in the LEON PS/2 Ctrl Registers.
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*/
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#define LEON_REG_PS2_CTRL_RE 0x00000001 /* Receiver enable */
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#define LEON_REG_PS2_CTRL_TE 0x00000002 /* Transmitter enable */
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#define LEON_REG_PS2_CTRL_RI 0x00000004 /* Keyboard receive irq */
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#define LEON_REG_PS2_CTRL_TI 0x00000008 /* Keyboard transmit irq */
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#define LEON3_IRQMPSTATUS_CPUNR 28
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#define LEON3_IRQMPSTATUS_BROADCAST 27
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#define GPTIMER_CONFIG_IRQNT(a) (((a) >> 3) & 0x1f)
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#define GPTIMER_CONFIG_ISSEP(a) ((a) & (1 << 8))
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#define GPTIMER_CONFIG_NTIMERS(a) ((a) & (0x7))
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#define LEON3_GPTIMER_CTRL_PENDING 0x10
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#define LEON3_GPTIMER_CONFIG_NRTIMERS(c) ((c)->config & 0x7)
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#define LEON3_GPTIMER_CTRL_ISPENDING(r) (((r)&LEON3_GPTIMER_CTRL_PENDING) ? 1 : 0)
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#ifdef CONFIG_SPARC_LEON
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#ifndef __ASSEMBLY__
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struct leon3_irqctrl_regs_map {
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u32 ilevel;
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u32 ipend;
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u32 iforce;
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u32 iclear;
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u32 mpstatus;
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u32 mpbroadcast;
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u32 notused02;
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u32 notused03;
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u32 ampctrl;
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u32 icsel[2];
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u32 notused13;
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u32 notused20;
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u32 notused21;
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u32 notused22;
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u32 notused23;
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u32 mask[16];
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u32 force[16];
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/* Extended IRQ registers */
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u32 intid[16]; /* 0xc0 */
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u32 unused[(0x1000-0x100)/4];
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};
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struct leon3_apbuart_regs_map {
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u32 data;
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u32 status;
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u32 ctrl;
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u32 scaler;
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};
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struct leon3_gptimerelem_regs_map {
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u32 val;
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u32 rld;
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u32 ctrl;
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u32 unused;
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};
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struct leon3_gptimer_regs_map {
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u32 scalar;
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u32 scalar_reload;
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u32 config;
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u32 unused;
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struct leon3_gptimerelem_regs_map e[8];
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};
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/*
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* Types and structure used for AMBA Plug & Play bus scanning
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*/
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#define AMBA_MAXAPB_DEVS 64
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#define AMBA_MAXAPB_DEVS_PERBUS 16
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struct amba_device_table {
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int devnr; /* number of devices on AHB or APB bus */
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unsigned int *addr[16]; /* addresses to the devices configuration tables */
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unsigned int allocbits[1]; /* 0=unallocated, 1=allocated driver */
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};
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struct amba_apbslv_device_table {
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int devnr; /* number of devices on AHB or APB bus */
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unsigned int *addr[AMBA_MAXAPB_DEVS]; /* addresses to the devices configuration tables */
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unsigned int apbmst[AMBA_MAXAPB_DEVS]; /* apb master if a entry is a apb slave */
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unsigned int apbmstidx[AMBA_MAXAPB_DEVS]; /* apb master idx if a entry is a apb slave */
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unsigned int allocbits[4]; /* 0=unallocated, 1=allocated driver */
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};
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struct amba_confarea_type {
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struct amba_confarea_type *next;/* next bus in chain */
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struct amba_device_table ahbmst;
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struct amba_device_table ahbslv;
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struct amba_apbslv_device_table apbslv;
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unsigned int apbmst;
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};
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/* collect apb slaves */
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struct amba_apb_device {
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unsigned int start, irq, bus_id;
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struct amba_confarea_type *bus;
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};
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/* collect ahb slaves */
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struct amba_ahb_device {
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unsigned int start[4], irq, bus_id;
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struct amba_confarea_type *bus;
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};
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struct device_node;
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void _amba_init(struct device_node *dp, struct device_node ***nextp);
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extern struct leon3_irqctrl_regs_map *leon3_irqctrl_regs;
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extern struct leon3_gptimer_regs_map *leon3_gptimer_regs;
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extern struct amba_apb_device leon_percpu_timer_dev[16];
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extern int leondebug_irq_disable;
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extern int leon_debug_irqout;
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extern unsigned long leon3_gptimer_irq;
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extern unsigned int sparc_leon_eirq;
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#endif /* __ASSEMBLY__ */
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#define LEON3_IO_AREA 0xfff00000
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#define LEON3_CONF_AREA 0xff000
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#define LEON3_AHB_SLAVE_CONF_AREA (1 << 11)
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#define LEON3_AHB_CONF_WORDS 8
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#define LEON3_APB_CONF_WORDS 2
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#define LEON3_AHB_MASTERS 16
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#define LEON3_AHB_SLAVES 16
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#define LEON3_APB_SLAVES 16
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#define LEON3_APBUARTS 8
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/* Vendor codes */
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#define VENDOR_GAISLER 1
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#define VENDOR_PENDER 2
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#define VENDOR_ESA 4
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#define VENDOR_OPENCORES 8
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/* Gaisler Research device id's */
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#define GAISLER_LEON3 0x003
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#define GAISLER_LEON3DSU 0x004
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#define GAISLER_ETHAHB 0x005
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#define GAISLER_APBMST 0x006
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#define GAISLER_AHBUART 0x007
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#define GAISLER_SRCTRL 0x008
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#define GAISLER_SDCTRL 0x009
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#define GAISLER_APBUART 0x00C
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#define GAISLER_IRQMP 0x00D
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#define GAISLER_AHBRAM 0x00E
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#define GAISLER_GPTIMER 0x011
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#define GAISLER_PCITRG 0x012
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#define GAISLER_PCISBRG 0x013
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#define GAISLER_PCIFBRG 0x014
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#define GAISLER_PCITRACE 0x015
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#define GAISLER_PCIDMA 0x016
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#define GAISLER_AHBTRACE 0x017
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#define GAISLER_ETHDSU 0x018
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#define GAISLER_PIOPORT 0x01A
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#define GAISLER_GRGPIO 0x01A
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#define GAISLER_AHBJTAG 0x01c
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#define GAISLER_ETHMAC 0x01D
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#define GAISLER_AHB2AHB 0x020
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#define GAISLER_USBDC 0x021
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#define GAISLER_ATACTRL 0x024
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#define GAISLER_DDRSPA 0x025
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#define GAISLER_USBEHC 0x026
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#define GAISLER_USBUHC 0x027
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#define GAISLER_I2CMST 0x028
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#define GAISLER_SPICTRL 0x02D
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#define GAISLER_DDR2SPA 0x02E
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#define GAISLER_SPIMCTRL 0x045
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#define GAISLER_LEON4 0x048
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#define GAISLER_LEON4DSU 0x049
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#define GAISLER_AHBSTAT 0x052
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#define GAISLER_FTMCTRL 0x054
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#define GAISLER_KBD 0x060
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#define GAISLER_VGA 0x061
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#define GAISLER_SVGA 0x063
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#define GAISLER_GRSYSMON 0x066
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#define GAISLER_GRACECTRL 0x067
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#define GAISLER_L2TIME 0xffd /* internal device: leon2 timer */
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#define GAISLER_L2C 0xffe /* internal device: leon2compat */
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#define GAISLER_PLUGPLAY 0xfff /* internal device: plug & play configarea */
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#define amba_vendor(x) (((x) >> 24) & 0xff)
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#define amba_device(x) (((x) >> 12) & 0xfff)
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#endif /* !defined(CONFIG_SPARC_LEON) */
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#endif
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