a3b90ad8d1
Some maros were not well aligned. Re-align them. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
104 lines
4.7 KiB
C
104 lines
4.7 KiB
C
/*
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* OMAP44xx PRCM MPU instance offset macros
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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*
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* Paul Walmsley (paul@pwsan.com)
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* Rajendra Nayak (rnayak@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
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* or "OMAP4430".
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
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#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
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#define OMAP4430_PRCM_MPU_BASE 0x48243000
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#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
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/* PRCM_MPU instances */
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#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
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#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
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#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
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#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
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/* PRCM_MPU clockdomain register offsets (from instance start) */
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#define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
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#define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
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/*
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* PRCM_MPU
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*
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* The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
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* point of view the PRCM_MPU is a single entity. It shares the same
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* programming model as the global PRCM and thus can be assimilate as two new
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* MOD inside the PRCM
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*/
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/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
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#define OMAP4_REVISION_PRCM_OFFSET 0x0000
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#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
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/* PRCM_MPU.DEVICE_PRM register offsets */
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#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
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#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
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#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
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#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
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/* PRCM_MPU.CPU0 register offsets */
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#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
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#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
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#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
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#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
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#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
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#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
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#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
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#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
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#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
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#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
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#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
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#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
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#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
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#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
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/* PRCM_MPU.CPU1 register offsets */
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#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
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#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
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#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
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#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
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#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
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#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
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#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
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#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
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#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
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#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
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#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
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#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
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#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
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#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
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/* Function prototypes */
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# ifndef __ASSEMBLER__
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extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
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extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
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extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
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s16 idx);
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# endif
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#endif
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