e17941b0c1
use x2apic id reported by cpuid during topology discovery, instead of the apic id configured in the APIC. For most of the systems, x2apic id reported by cpuid leaf 0xb will be same as the physical apic id reported by the APIC_ID register of the APIC. We follow the suggested guidelines and use the apic id reported by the cpuid. No change to non-generic UV platforms, will use the apic id reported in the APIC_ID register as the cpuid reported apic id's may not be unique. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
160 lines
3.4 KiB
C
160 lines
3.4 KiB
C
#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/dmar.h>
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#include <asm/smp.h>
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#include <asm/ipi.h>
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#include <asm/genapic.h>
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DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
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static int __init x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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if (cpu_has_x2apic && intr_remapping_enabled)
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return 1;
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return 0;
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}
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/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
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static cpumask_t x2apic_target_cpus(void)
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{
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return cpumask_of_cpu(0);
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}
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/*
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* for now each logical cpu is in its own vector allocation domain.
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*/
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static cpumask_t x2apic_vector_allocation_domain(int cpu)
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{
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cpumask_t domain = CPU_MASK_NONE;
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cpu_set(cpu, domain);
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return domain;
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}
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static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
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unsigned int dest)
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{
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unsigned long cfg;
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cfg = __prepare_ICR(0, vector, dest);
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/*
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* send the IPI.
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*/
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x2apic_icr_write(cfg, apicid);
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}
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/*
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* for now, we send the IPI's one by one in the cpumask.
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* TBD: Based on the cpu mask, we can send the IPI's to the cluster group
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* at once. We have 16 cpu's in a cluster. This will minimize IPI register
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* writes.
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*/
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static void x2apic_send_IPI_mask(cpumask_t mask, int vector)
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{
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unsigned long flags;
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unsigned long query_cpu;
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local_irq_save(flags);
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for_each_cpu_mask(query_cpu, mask) {
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__x2apic_send_IPI_dest(per_cpu(x86_cpu_to_logical_apicid, query_cpu),
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vector, APIC_DEST_LOGICAL);
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}
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local_irq_restore(flags);
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}
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static void x2apic_send_IPI_allbutself(int vector)
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{
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cpumask_t mask = cpu_online_map;
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cpu_clear(smp_processor_id(), mask);
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if (!cpus_empty(mask))
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x2apic_send_IPI_mask(mask, vector);
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}
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static void x2apic_send_IPI_all(int vector)
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{
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x2apic_send_IPI_mask(cpu_online_map, vector);
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}
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static int x2apic_apic_id_registered(void)
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{
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return 1;
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}
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static unsigned int x2apic_cpu_mask_to_apicid(cpumask_t cpumask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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cpu = first_cpu(cpumask);
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if ((unsigned)cpu < NR_CPUS)
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return per_cpu(x86_cpu_to_logical_apicid, cpu);
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else
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return BAD_APICID;
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}
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static unsigned int get_apic_id(unsigned long x)
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{
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unsigned int id;
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id = x;
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return id;
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}
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static unsigned long set_apic_id(unsigned int id)
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{
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unsigned long x;
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x = id;
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return x;
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}
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static unsigned int phys_pkg_id(int index_msb)
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{
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return current_cpu_data.initial_apicid >> index_msb;
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}
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static void x2apic_send_IPI_self(int vector)
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{
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apic_write(APIC_SELF_IPI, vector);
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}
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static void init_x2apic_ldr(void)
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{
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int cpu = smp_processor_id();
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per_cpu(x86_cpu_to_logical_apicid, cpu) = apic_read(APIC_LDR);
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return;
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}
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struct genapic apic_x2apic_cluster = {
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.name = "cluster x2apic",
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.acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
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.int_delivery_mode = dest_LowestPrio,
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.int_dest_mode = (APIC_DEST_LOGICAL != 0),
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.target_cpus = x2apic_target_cpus,
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.vector_allocation_domain = x2apic_vector_allocation_domain,
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.apic_id_registered = x2apic_apic_id_registered,
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.init_apic_ldr = init_x2apic_ldr,
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.send_IPI_all = x2apic_send_IPI_all,
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.send_IPI_allbutself = x2apic_send_IPI_allbutself,
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.send_IPI_mask = x2apic_send_IPI_mask,
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.send_IPI_self = x2apic_send_IPI_self,
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.cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
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.phys_pkg_id = phys_pkg_id,
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.get_apic_id = get_apic_id,
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.set_apic_id = set_apic_id,
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.apic_id_mask = (0xFFFFFFFFu),
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};
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