9a8fd55899
The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
35 lines
679 B
C
35 lines
679 B
C
/*
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* include/asm-xtensa/ipc.h
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of
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* this archive for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_IPC_H
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#define _XTENSA_IPC_H
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struct ipc_kludge {
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struct msgbuf __user *msgp;
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long msgtyp;
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};
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#define SEMOP 1
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#define SEMGET 2
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#define SEMCTL 3
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#define SEMTIMEDOP 4
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#define MSGSND 11
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#define MSGRCV 12
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#define MSGGET 13
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#define MSGCTL 14
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#define SHMAT 21
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#define SHMDT 22
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#define SHMGET 23
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#define SHMCTL 24
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#define IPCCALL(version,op) ((version)<<16 | (op))
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#endif /* _XTENSA_IPC_H */
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