44e4e196a9
We used cache_line as cache_line_lenght. For this reason we did cache flushing 4 times longer than was necessary. Signed-off-by: Michal Simek <monstr@monstr.eu>
256 lines
5.2 KiB
C
256 lines
5.2 KiB
C
/*
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* Cache control for MicroBlaze cache memories
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*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2007 John Williams <john.williams@petalogix.com>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#include <asm/cacheflush.h>
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#include <linux/cache.h>
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#include <asm/cpuinfo.h>
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/* Exported functions */
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void _enable_icache(void)
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{
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if (cpuinfo.use_icache) {
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#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
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__asm__ __volatile__ (" \
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msrset r0, %0; \
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nop; " \
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: \
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: "i" (MSR_ICE) \
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: "memory");
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#else
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__asm__ __volatile__ (" \
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mfs r12, rmsr; \
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nop; \
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ori r12, r12, %0; \
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mts rmsr, r12; \
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nop; " \
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: \
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: "i" (MSR_ICE) \
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: "memory", "r12");
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#endif
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}
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}
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void _disable_icache(void)
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{
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if (cpuinfo.use_icache) {
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#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
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__asm__ __volatile__ (" \
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msrclr r0, %0; \
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nop; " \
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: \
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: "i" (MSR_ICE) \
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: "memory");
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#else
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__asm__ __volatile__ (" \
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mfs r12, rmsr; \
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nop; \
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andi r12, r12, ~%0; \
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mts rmsr, r12; \
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nop; " \
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: \
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: "i" (MSR_ICE) \
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: "memory", "r12");
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#endif
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}
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}
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void _invalidate_icache(unsigned int addr)
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{
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if (cpuinfo.use_icache) {
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__asm__ __volatile__ (" \
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wic %0, r0" \
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: \
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: "r" (addr));
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}
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}
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void _enable_dcache(void)
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{
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if (cpuinfo.use_dcache) {
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#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
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__asm__ __volatile__ (" \
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msrset r0, %0; \
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nop; " \
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: \
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: "i" (MSR_DCE) \
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: "memory");
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#else
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__asm__ __volatile__ (" \
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mfs r12, rmsr; \
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nop; \
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ori r12, r12, %0; \
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mts rmsr, r12; \
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nop; " \
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: \
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: "i" (MSR_DCE) \
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: "memory", "r12");
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#endif
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}
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}
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void _disable_dcache(void)
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{
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#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
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__asm__ __volatile__ (" \
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msrclr r0, %0; \
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nop; " \
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: \
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: "i" (MSR_DCE) \
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: "memory");
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#else
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__asm__ __volatile__ (" \
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mfs r12, rmsr; \
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nop; \
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andi r12, r12, ~%0; \
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mts rmsr, r12; \
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nop; " \
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: \
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: "i" (MSR_DCE) \
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: "memory", "r12");
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#endif
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}
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void _invalidate_dcache(unsigned int addr)
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{
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__asm__ __volatile__ (" \
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wdc %0, r0" \
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: \
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: "r" (addr));
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}
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void __invalidate_icache_all(void)
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{
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unsigned int i;
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unsigned flags;
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if (cpuinfo.use_icache) {
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local_irq_save(flags);
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__disable_icache();
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/* Just loop through cache size and invalidate, no need to add
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CACHE_BASE address */
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for (i = 0; i < cpuinfo.icache_size;
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i += cpuinfo.icache_line_length)
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__invalidate_icache(i);
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__enable_icache();
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local_irq_restore(flags);
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}
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}
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void __invalidate_icache_range(unsigned long start, unsigned long end)
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{
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unsigned int i;
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unsigned flags;
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unsigned int align;
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if (cpuinfo.use_icache) {
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/*
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* No need to cover entire cache range,
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* just cover cache footprint
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*/
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end = min(start + cpuinfo.icache_size, end);
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align = ~(cpuinfo.icache_line_length - 1);
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start &= align; /* Make sure we are aligned */
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/* Push end up to the next cache line */
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end = ((end & align) + cpuinfo.icache_line_length);
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local_irq_save(flags);
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__disable_icache();
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for (i = start; i < end; i += cpuinfo.icache_line_length)
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__invalidate_icache(i);
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__enable_icache();
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local_irq_restore(flags);
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}
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}
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void __invalidate_icache_page(struct vm_area_struct *vma, struct page *page)
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{
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__invalidate_icache_all();
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}
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void __invalidate_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long adr,
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int len)
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{
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__invalidate_icache_all();
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}
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void __invalidate_cache_sigtramp(unsigned long addr)
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{
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__invalidate_icache_range(addr, addr + 8);
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}
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void __invalidate_dcache_all(void)
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{
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unsigned int i;
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unsigned flags;
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if (cpuinfo.use_dcache) {
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local_irq_save(flags);
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__disable_dcache();
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/*
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* Just loop through cache size and invalidate,
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* no need to add CACHE_BASE address
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*/
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for (i = 0; i < cpuinfo.dcache_size;
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i += cpuinfo.dcache_line_length)
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__invalidate_dcache(i);
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__enable_dcache();
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local_irq_restore(flags);
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}
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}
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void __invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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unsigned int i;
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unsigned flags;
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unsigned int align;
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if (cpuinfo.use_dcache) {
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/*
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* No need to cover entire cache range,
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* just cover cache footprint
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*/
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end = min(start + cpuinfo.dcache_size, end);
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align = ~(cpuinfo.dcache_line_length - 1);
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start &= align; /* Make sure we are aligned */
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/* Push end up to the next cache line */
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end = ((end & align) + cpuinfo.dcache_line_length);
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local_irq_save(flags);
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__disable_dcache();
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for (i = start; i < end; i += cpuinfo.dcache_line_length)
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__invalidate_dcache(i);
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__enable_dcache();
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local_irq_restore(flags);
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}
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}
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void __invalidate_dcache_page(struct vm_area_struct *vma, struct page *page)
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{
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__invalidate_dcache_all();
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}
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void __invalidate_dcache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long adr,
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int len)
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{
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__invalidate_dcache_all();
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}
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