df3b861155
The tlb invalidates in kmap_atomic/kunmap_atomic can be called from IRQ context, however they are only local invalidates (on the processor that the kmap was called on). In the future we want to use IPIs to do tlb invalidates this causes issue since flush_tlb_page() is considered a broadcast invalidate. Add local_flush_tlb_page() as a non-broadcast invalidate and use it in kmap_atomic() since we don't have enough information in the flush_tlb_page() call to determine its local. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
184 lines
4.7 KiB
C
184 lines
4.7 KiB
C
#ifndef _ASM_POWERPC_TLBFLUSH_H
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#define _ASM_POWERPC_TLBFLUSH_H
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/*
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* TLB flushing:
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*
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - local_flush_tlb_page(vmaddr) flushes one page on the local processor
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* - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifdef __KERNEL__
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#if defined(CONFIG_4xx) || defined(CONFIG_8xx) || defined(CONFIG_FSL_BOOKE)
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/*
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* TLB flushing for software loaded TLB chips
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*
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* TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range &
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* flush_tlb_kernel_range are best implemented as tlbia vs
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* specific tlbie's
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*/
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#include <linux/mm.h>
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extern void _tlbie(unsigned long address, unsigned int pid);
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extern void _tlbil_all(void);
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extern void _tlbil_pid(unsigned int pid);
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extern void _tlbil_va(unsigned long address, unsigned int pid);
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#if defined(CONFIG_40x) || defined(CONFIG_8xx)
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#define _tlbia() asm volatile ("tlbia; sync" : : : "memory")
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#else /* CONFIG_44x || CONFIG_FSL_BOOKE */
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extern void _tlbia(void);
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#endif
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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_tlbil_pid(mm->context.id);
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}
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static inline void local_flush_tlb_page(unsigned long vmaddr)
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{
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_tlbil_va(vmaddr, 0);
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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_tlbil_va(vmaddr, vma ? vma->vm_mm->context.id : 0);
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}
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static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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flush_tlb_page(vma, vmaddr);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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_tlbil_pid(vma->vm_mm->context.id);
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}
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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{
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_tlbil_pid(0);
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}
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#elif defined(CONFIG_PPC32)
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/*
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* TLB flushing for "classic" hash-MMMU 32-bit CPUs, 6xx, 7xx, 7xxx
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*/
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extern void _tlbie(unsigned long address);
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extern void _tlbia(void);
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extern void flush_tlb_mm(struct mm_struct *mm);
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extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
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extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
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extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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static inline void local_flush_tlb_page(unsigned long vmaddr)
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{
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flush_tlb_page(NULL, vmaddr);
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}
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#else
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/*
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* TLB flushing for 64-bit has-MMU CPUs
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*/
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#include <linux/percpu.h>
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#include <asm/page.h>
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#define PPC64_TLB_BATCH_NR 192
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struct ppc64_tlb_batch {
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int active;
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unsigned long index;
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struct mm_struct *mm;
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real_pte_t pte[PPC64_TLB_BATCH_NR];
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unsigned long vaddr[PPC64_TLB_BATCH_NR];
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unsigned int psize;
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int ssize;
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};
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DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
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extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
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extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, unsigned long pte, int huge);
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#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
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static inline void arch_enter_lazy_mmu_mode(void)
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{
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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batch->active = 1;
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}
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static inline void arch_leave_lazy_mmu_mode(void)
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{
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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if (batch->index)
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__flush_tlb_pending(batch);
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batch->active = 0;
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}
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#define arch_flush_lazy_mmu_mode() do {} while (0)
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extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize,
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int ssize, int local);
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extern void flush_hash_range(unsigned long number, int local);
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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}
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static inline void local_flush_tlb_page(unsigned long vmaddr)
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{
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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}
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static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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}
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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{
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}
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/* Private function for use by PCI IO mapping code */
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extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
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unsigned long end);
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#endif
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#endif /*__KERNEL__ */
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#endif /* _ASM_POWERPC_TLBFLUSH_H */
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