1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
128 lines
3.7 KiB
C
128 lines
3.7 KiB
C
/*
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* arch/v850/kernel/v850e2_cache.c -- Cache control for V850E2 cache
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* memories
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*
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* Copyright (C) 2003 NEC Electronics Corporation
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* Copyright (C) 2003 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#include <linux/mm.h>
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#include <asm/v850e2_cache.h>
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/* Cache operations we can do. The encoding corresponds directly to the
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value we need to write into the COPR register. */
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enum cache_op {
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OP_SYNC_IF_DIRTY = V850E2_CACHE_COPR_CFC(0), /* 000 */
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OP_SYNC_IF_VALID = V850E2_CACHE_COPR_CFC(1), /* 001 */
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OP_SYNC_IF_VALID_AND_CLEAR = V850E2_CACHE_COPR_CFC(3), /* 011 */
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OP_WAY_CLEAR = V850E2_CACHE_COPR_CFC(4), /* 100 */
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OP_FILL = V850E2_CACHE_COPR_CFC(5), /* 101 */
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OP_CLEAR = V850E2_CACHE_COPR_CFC(6), /* 110 */
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OP_CREATE_DIRTY = V850E2_CACHE_COPR_CFC(7) /* 111 */
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};
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/* Which cache to use. This encoding also corresponds directly to the
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value we need to write into the COPR register. */
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enum cache {
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ICACHE = 0,
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DCACHE = V850E2_CACHE_COPR_LBSL
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};
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/* Returns ADDR rounded down to the beginning of its cache-line. */
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#define CACHE_LINE_ADDR(addr) \
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((addr) & ~(V850E2_CACHE_LINE_SIZE - 1))
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/* Returns END_ADDR rounded up to the `limit' of its cache-line. */
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#define CACHE_LINE_END_ADDR(end_addr) \
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CACHE_LINE_ADDR(end_addr + (V850E2_CACHE_LINE_SIZE - 1))
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/* Low-level cache ops. */
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/* Apply cache-op OP to all entries in CACHE. */
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static inline void cache_op_all (enum cache_op op, enum cache cache)
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{
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int cmd = op | cache | V850E2_CACHE_COPR_WSLE | V850E2_CACHE_COPR_STRT;
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if (op != OP_WAY_CLEAR) {
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/* The WAY_CLEAR operation does the whole way, but other
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ops take begin-index and count params; we just indicate
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the entire cache. */
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V850E2_CACHE_CADL = 0;
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V850E2_CACHE_CADH = 0;
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V850E2_CACHE_CCNT = V850E2_CACHE_WAY_SIZE - 1;
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}
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V850E2_CACHE_COPR = cmd | V850E2_CACHE_COPR_WSL(0); /* way 0 */
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V850E2_CACHE_COPR = cmd | V850E2_CACHE_COPR_WSL(1); /* way 1 */
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V850E2_CACHE_COPR = cmd | V850E2_CACHE_COPR_WSL(2); /* way 2 */
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V850E2_CACHE_COPR = cmd | V850E2_CACHE_COPR_WSL(3); /* way 3 */
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}
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/* Apply cache-op OP to all entries in CACHE covering addresses ADDR
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through ADDR+LEN. */
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static inline void cache_op_range (enum cache_op op, u32 addr, u32 len,
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enum cache cache)
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{
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u32 start = CACHE_LINE_ADDR (addr);
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u32 end = CACHE_LINE_END_ADDR (addr + len);
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u32 num_lines = (end - start) >> V850E2_CACHE_LINE_SIZE_BITS;
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V850E2_CACHE_CADL = start & 0xFFFF;
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V850E2_CACHE_CADH = start >> 16;
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V850E2_CACHE_CCNT = num_lines - 1;
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V850E2_CACHE_COPR = op | cache | V850E2_CACHE_COPR_STRT;
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}
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/* High-level ops. */
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static void cache_exec_after_store_all (void)
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{
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cache_op_all (OP_SYNC_IF_DIRTY, DCACHE);
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cache_op_all (OP_WAY_CLEAR, ICACHE);
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}
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static void cache_exec_after_store_range (u32 start, u32 len)
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{
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cache_op_range (OP_SYNC_IF_DIRTY, start, len, DCACHE);
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cache_op_range (OP_CLEAR, start, len, ICACHE);
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}
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/* Exported functions. */
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void flush_icache (void)
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{
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cache_exec_after_store_all ();
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}
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void flush_icache_range (unsigned long start, unsigned long end)
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{
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cache_exec_after_store_range (start, end - start);
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}
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void flush_icache_page (struct vm_area_struct *vma, struct page *page)
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{
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cache_exec_after_store_range (page_to_virt (page), PAGE_SIZE);
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}
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void flush_icache_user_range (struct vm_area_struct *vma, struct page *page,
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unsigned long addr, int len)
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{
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cache_exec_after_store_range (addr, len);
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}
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void flush_cache_sigtramp (unsigned long addr)
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{
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/* For the exact size, see signal.c, but 16 bytes should be enough. */
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cache_exec_after_store_range (addr, 16);
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}
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