b7d4581844
According to Appendix F, the TLB is the primary arbiter of speculation. Thus, if a page has a TLB entry, it may be speculatively read into the cache. On linux, this can cause us incoherencies because if we're about to do a disk read, we call get_user_pages() to do the flush/invalidate in user space, but we still potentially have the user TLB entries, and the cache could speculate the lines back into userspace (thus causing stale data to be used). This is fixed by purging the TLB entries before we flush through the tmpalias space. Now, the only way the line could be re-speculated is if the user actually tries to touch it (which is not allowed). Signed-off-by: James Bottomley <James.Bottomley@suse.de>
162 lines
4.8 KiB
C
162 lines
4.8 KiB
C
#ifndef _PARISC_CACHEFLUSH_H
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#define _PARISC_CACHEFLUSH_H
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#include <linux/mm.h>
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#include <linux/uaccess.h>
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#include <asm/tlbflush.h>
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/* The usual comment is "Caches aren't brain-dead on the <architecture>".
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* Unfortunately, that doesn't apply to PA-RISC. */
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/* Internal implementation */
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void flush_data_cache_local(void *); /* flushes local data-cache only */
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void flush_instruction_cache_local(void *); /* flushes local code-cache only */
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#ifdef CONFIG_SMP
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void flush_data_cache(void); /* flushes data-cache only (all processors) */
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void flush_instruction_cache(void); /* flushes i-cache only (all processors) */
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#else
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#define flush_data_cache() flush_data_cache_local(NULL)
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#define flush_instruction_cache() flush_instruction_cache_local(NULL)
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#endif
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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void flush_user_icache_range_asm(unsigned long, unsigned long);
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void flush_kernel_icache_range_asm(unsigned long, unsigned long);
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void flush_user_dcache_range_asm(unsigned long, unsigned long);
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void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
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void flush_kernel_dcache_page_asm(void *);
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void flush_kernel_icache_page(void *);
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void flush_user_dcache_range(unsigned long, unsigned long);
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void flush_user_icache_range(unsigned long, unsigned long);
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/* Cache flush operations */
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void flush_cache_all_local(void);
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void flush_cache_all(void);
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void flush_cache_mm(struct mm_struct *mm);
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#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
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void flush_kernel_dcache_page_addr(void *addr);
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static inline void flush_kernel_dcache_page(struct page *page)
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{
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flush_kernel_dcache_page_addr(page_address(page));
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}
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#define flush_kernel_dcache_range(start,size) \
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flush_kernel_dcache_range_asm((start), (start)+(size));
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/* vmap range flushes and invalidates. Architecturally, we don't need
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* the invalidate, because the CPU should refuse to speculate once an
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* area has been flushed, so invalidate is left empty */
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static inline void flush_kernel_vmap_range(void *vaddr, int size)
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{
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unsigned long start = (unsigned long)vaddr;
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flush_kernel_dcache_range_asm(start, start + size);
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}
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static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
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{
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unsigned long start = (unsigned long)vaddr;
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void *cursor = vaddr;
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for ( ; cursor < vaddr + size; cursor += PAGE_SIZE) {
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struct page *page = vmalloc_to_page(cursor);
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if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
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flush_kernel_dcache_page(page);
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}
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flush_kernel_dcache_range_asm(start, start + size);
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}
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vunmap(start, end) flush_cache_all()
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *page);
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#define flush_dcache_mmap_lock(mapping) \
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spin_lock_irq(&(mapping)->tree_lock)
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#define flush_dcache_mmap_unlock(mapping) \
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spin_unlock_irq(&(mapping)->tree_lock)
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#define flush_icache_page(vma,page) do { \
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flush_kernel_dcache_page(page); \
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flush_kernel_icache_page(page_address(page)); \
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} while (0)
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#define flush_icache_range(s,e) do { \
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flush_kernel_dcache_range_asm(s,e); \
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flush_kernel_icache_range_asm(s,e); \
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} while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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flush_cache_page(vma, vaddr, page_to_pfn(page)); \
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memcpy(dst, src, len); \
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flush_kernel_dcache_range_asm((unsigned long)dst, (unsigned long)dst + len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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flush_cache_page(vma, vaddr, page_to_pfn(page)); \
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memcpy(dst, src, len); \
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} while (0)
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void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn);
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void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end);
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/* defined in pacache.S exported in cache.c used by flush_anon_page */
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void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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#define ARCH_HAS_FLUSH_ANON_PAGE
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static inline void
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flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
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{
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if (PageAnon(page)) {
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flush_tlb_page(vma, vmaddr);
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flush_dcache_page_asm(page_to_phys(page), vmaddr);
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}
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}
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#ifdef CONFIG_DEBUG_RODATA
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void mark_rodata_ro(void);
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#endif
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#ifdef CONFIG_PA8X00
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/* Only pa8800, pa8900 needs this */
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#include <asm/kmap_types.h>
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#define ARCH_HAS_KMAP
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void kunmap_parisc(void *addr);
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static inline void *kmap(struct page *page)
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{
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might_sleep();
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return page_address(page);
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}
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#define kunmap(page) kunmap_parisc(page_address(page))
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static inline void *__kmap_atomic(struct page *page)
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{
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pagefault_disable();
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return page_address(page);
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}
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static inline void __kunmap_atomic(void *addr)
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{
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kunmap_parisc(addr);
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pagefault_enable();
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}
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#define kmap_atomic_prot(page, prot) kmap_atomic(page)
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#define kmap_atomic_pfn(pfn) kmap_atomic(pfn_to_page(pfn))
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#define kmap_atomic_to_page(ptr) virt_to_page(ptr)
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#endif
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#endif /* _PARISC_CACHEFLUSH_H */
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